sap_1_tb_settings.txt

来自「這是用verilog寫的一個簡單的處理器」· 文本 代码 · 共 31 行

[SETTINGS]
UUT_module%SAP_1%
TB_module%SAP_1_tb%
DSN_PATH%$DSN\src\TestBench%
OUTPUT_DIRECTORY%C:\My_Designs\sap1\src\TestBench%
STIMULUS%NO%
VECTORS_FILE%%
AWF_FILE%%
TB_FILE%SAP_1_TB.v%
MACRO_FILE%SAP_1_TB_runtest.do%
UUT_module_FILE%SAP_1.v%
LIBRARY_NAME%sap1%
LIBRARY_TYPE%work%
TestBench_TYPE%simple%
ENABLE_FILE%none%

[GENERICS]

[PORTS]
asy_rst%in%wire%NO%NOCLK%
clk%in%wire%NO%NOCLK%
Oreg%out%[7:0]reg%NO%NOCLK%
go%in%wire%NO%NOCLK%

[SDF]

[INCLUDE]
[Verilog_FILES]
$DSN\src\SAP_1.v