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# Schematic : PDCL (jhdparse) # Schematic : PDCL (jhdparse) # Schematic : PDCL (jhdparse) # Schematic : PDCL (jhdparse) # Schematic : View Verilog Functional Model andnor2.vf # Schematic : View

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//! ************************************************************************** // Written by: Map H.39 on Fri Mar 25 06:54:49 2005 //! ***************************************************************

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{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0}

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3} { "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info:

JDF B // Created by Version 5.1 PROJECT GAL_300F DESIGN gal_300f Normal DEVKIT GAL16V8D-25QJ ENTRY Schematic/VHDL MODULE addr_select.vhd MODSTYLE ADDR_SELECT Normal MODULE gal_300f.sch MODST

FILE_TYPE = EXPANDEDNETLIST; { Using PSTWRITER 14.2 P007Mar-15-2005 at 12:42:16 } NET_NAME 'LCD_DB7' '@SPARTAN3_DDR1.SCHEMATIC1(SCH_1):LCD_DB7': C_SIGNAL='@spartan3_ddr1.schematic1(sch_1):lcd_db7';

Checking Pins and Pin Connections -------------------------------------------------- Checking Schematic: SCHEMATIC1 -------------------------------------------------- Checking Electrical Rules

//! ************************************************************************** // Written by: Map H.42 on Fri Mar 13 15:28:19 2009 //! ***************************************************************