sled.map.qmsg

很多vhdl例程代码

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 168 06/22/2005 Service Pack 1.04 SJ Full Version " "Info: Version 5.0 Build 168 06/22/2005 Service Pack 1.04 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Fri Sep 15 15:26:31 2006 " "Info: Processing started: Fri Sep 15 15:26:31 2006" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off sled -c sled " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off sled -c sled" {  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "decl7s.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file decl7s.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 decl7s-ONE " "Info: Found design unit 1: decl7s-ONE" {  } { { "decl7s.vhd" "" { Text "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/decl7s.vhd" 33 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 decl7s " "Info: Found entity 1: decl7s" {  } { { "decl7s.vhd" "" { Text "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/decl7s.vhd" 26 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "sled.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file sled.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 sled " "Info: Found entity 1: sled" {  } { { "sled.bdf" "" { Schematic "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/sled.bdf" { } } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "sled " "Info: Elaborating entity \"sled\" for the top level hierarchy" {  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "decl7s decl7s:inst " "Info: Elaborating entity \"decl7s\" for hierarchy \"decl7s:inst\"" {  } { { "sled.bdf" "inst" { Schematic "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/sled.bdf" { { 56 416 544 152 "inst" "" } } } }  } 0}
{ "Info" "IVRFX_VHDL_CASE_STATEMENT_OTHERS_CLAUSE_NEVER_SELECTED" "decl7s.vhd(56) " "Info: VHDL Case Statement information at decl7s.vhd(56): OTHERS choice is never selected" {  } { { "decl7s.vhd" "" { Text "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/decl7s.vhd" 56 0 0 } }  } 0}
{ "Info" "ISGN_SEARCH_FILE" "counter.vhd 2 1 " "Info: Using design file counter.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 counter-SYN " "Info: Found design unit 1: counter-SYN" {  } { { "counter.vhd" "" { Text "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/counter.vhd" 48 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 counter " "Info: Found entity 1: counter" {  } { { "counter.vhd" "" { Text "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/counter.vhd" 39 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "counter counter:inst2 " "Info: Elaborating entity \"counter\" for hierarchy \"counter:inst2\"" {  } { { "sled.bdf" "inst2" { Schematic "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/sled.bdf" { { 48 232 376 112 "inst2" "" } } } }  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/quartus50/libraries/megafunctions/lpm_counter.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus50/libraries/megafunctions/lpm_counter.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_counter " "Info: Found entity 1: lpm_counter" {  } { { "lpm_counter.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/lpm_counter.tdf" 227 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_counter counter:inst2\|lpm_counter:lpm_counter_component " "Info: Elaborating entity \"lpm_counter\" for hierarchy \"counter:inst2\|lpm_counter:lpm_counter_component\"" {  } { { "counter.vhd" "lpm_counter_component" { Text "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/counter.vhd" 69 -1 0 } }  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cntr_cs6.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/cntr_cs6.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cntr_cs6 " "Info: Found entity 1: cntr_cs6" {  } { { "db/cntr_cs6.tdf" "" { Text "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/db/cntr_cs6.tdf" 25 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cntr_cs6 counter:inst2\|lpm_counter:lpm_counter_component\|cntr_cs6:auto_generated " "Info: Elaborating entity \"cntr_cs6\" for hierarchy \"counter:inst2\|lpm_counter:lpm_counter_component\|cntr_cs6:auto_generated\"" {  } { { "lpm_counter.tdf" "auto_generated" { Text "c:/altera/quartus50/libraries/megafunctions/lpm_counter.tdf" 251 3 0 } }  } 0}
{ "Info" "ISGN_SEARCH_FILE" "int_div.vhd 2 1 " "Info: Using design file int_div.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 int_div-Devider " "Info: Found design unit 1: int_div-Devider" {  } { { "int_div.vhd" "" { Text "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/int_div.vhd" 36 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 int_div " "Info: Found entity 1: int_div" {  } { { "int_div.vhd" "" { Text "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/int_div.vhd" 27 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "int_div int_div:inst1 " "Info: Elaborating entity \"int_div\" for hierarchy \"int_div:inst1\"" {  } { { "sled.bdf" "inst1" { Schematic "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/sled.bdf" { { 48 72 208 144 "inst1" "" } } } }  } 0}
{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "dig\[7\] GND " "Warning: Pin \"dig\[7\]\" stuck at GND" {  } { { "sled.bdf" "" { Schematic "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/sled.bdf" { { 232 440 616 248 "dig\[7..0\]" "" } } } }  } 0} { "Warning" "WOPT_MLS_STUCK_PIN" "dig\[6\] GND " "Warning: Pin \"dig\[6\]\" stuck at GND" {  } { { "sled.bdf" "" { Schematic "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/sled.bdf" { { 232 440 616 248 "dig\[7..0\]" "" } } } }  } 0} { "Warning" "WOPT_MLS_STUCK_PIN" "dig\[5\] GND " "Warning: Pin \"dig\[5\]\" stuck at GND" {  } { { "sled.bdf" "" { Schematic "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/sled.bdf" { { 232 440 616 248 "dig\[7..0\]" "" } } } }  } 0} { "Warning" "WOPT_MLS_STUCK_PIN" "dig\[4\] GND " "Warning: Pin \"dig\[4\]\" stuck at GND" {  } { { "sled.bdf" "" { Schematic "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/sled.bdf" { { 232 440 616 248 "dig\[7..0\]" "" } } } }  } 0} { "Warning" "WOPT_MLS_STUCK_PIN" "dig\[3\] GND " "Warning: Pin \"dig\[3\]\" stuck at GND" {  } { { "sled.bdf" "" { Schematic "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/sled.bdf" { { 232 440 616 248 "dig\[7..0\]" "" } } } }  } 0} { "Warning" "WOPT_MLS_STUCK_PIN" "dig\[2\] GND " "Warning: Pin \"dig\[2\]\" stuck at GND" {  } { { "sled.bdf" "" { Schematic "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/sled.bdf" { { 232 440 616 248 "dig\[7..0\]" "" } } } }  } 0} { "Warning" "WOPT_MLS_STUCK_PIN" "dig\[1\] GND " "Warning: Pin \"dig\[1\]\" stuck at GND" {  } { { "sled.bdf" "" { Schematic "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/sled.bdf" { { 232 440 616 248 "dig\[7..0\]" "" } } } }  } 0} { "Warning" "WOPT_MLS_STUCK_PIN" "dig\[0\] GND " "Warning: Pin \"dig\[0\]\" stuck at GND" {  } { { "sled.bdf" "" { Schematic "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/sled.bdf" { { 232 440 616 248 "dig\[7..0\]" "" } } } }  } 0} { "Warning" "WOPT_MLS_STUCK_PIN" "seg\[7\] VCC " "Warning: Pin \"seg\[7\]\" stuck at VCC" {  } { { "sled.bdf" "" { Schematic "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/sled.bdf" { { 80 600 776 96 "seg\[7..0\]" "" } } } }  } 0}  } {  } 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "99 " "Info: Implemented 99 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "1 " "Info: Implemented 1 input pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_OPINS" "16 " "Info: Implemented 16 output pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_LCELLS" "82 " "Info: Implemented 82 logic cells" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 10 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 10 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Fri Sep 15 15:26:34 2006 " "Info: Processing ended: Fri Sep 15 15:26:34 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Info: Elapsed time: 00:00:04" {  } {  } 0}  } {  } 0}