gal_300f.syn

一个组合逻辑实例,完成地址选择,读写信号产生等时序

JDF B
// Created by Version 5.1 
PROJECT GAL_300F
DESIGN gal_300f Normal
DEVKIT GAL16V8D-25QJ
ENTRY Schematic/VHDL
MODULE addr_select.vhd
MODSTYLE ADDR_SELECT Normal
MODULE gal_300f.sch
MODSTYLE gal_300f Normal
SYNTHESIS_TOOL Synplify