crc2.map.qmsg

基于FPGA的1CRC_16校验基于FPGA的1CRC_16校验基于FPGA的1CRC_16校验

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.2 Build 151 09/26/2007 SJ Full Version " "Info: Version 7.2 Build 151 09/26/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Wed Oct 15 01:40:09 2008 " "Info: Processing started: Wed Oct 15 01:40:09 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off crc2 -c crc2 " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off crc2 -c crc2" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../crc/crc.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file ../crc/crc.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 crc-a " "Info: Found design unit 1: crc-a" {  } { { "../crc/crc.vhd" "" { Text "F:/FPGA_CHENGXU/crc/crc.vhd" 8 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 crc " "Info: Found entity 1: crc" {  } { { "../crc/crc.vhd" "" { Text "F:/FPGA_CHENGXU/crc/crc.vhd" 3 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "crc2.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file crc2.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 crc2 " "Info: Found entity 1: crc2" {  } { { "crc2.bdf" "" { Schematic "F:/FPGA_CHENGXU/crc2/crc2.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../second/crc_and.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file ../second/crc_and.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 crc_and-a " "Info: Found design unit 1: crc_and-a" {  } { { "../second/crc_and.vhd" "" { Text "F:/FPGA_CHENGXU/second/crc_and.vhd" 10 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 crc_and " "Info: Found entity 1: crc_and" {  } { { "../second/crc_and.vhd" "" { Text "F:/FPGA_CHENGXU/second/crc_and.vhd" 3 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "crc_j.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file crc_j.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 crc_j-a " "Info: Found design unit 1: crc_j-a" {  } { { "crc_j.vhd" "" { Text "F:/FPGA_CHENGXU/crc2/crc_j.vhd" 8 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 crc_j " "Info: Found entity 1: crc_j" {  } { { "crc_j.vhd" "" { Text "F:/FPGA_CHENGXU/crc2/crc_j.vhd" 3 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "crc_p.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file crc_p.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 crc_p-a " "Info: Found design unit 1: crc_p-a" {  } { { "crc_p.vhd" "" { Text "F:/FPGA_CHENGXU/crc2/crc_p.vhd" 11 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 crc_p " "Info: Found entity 1: crc_p" {  } { { "crc_p.vhd" "" { Text "F:/FPGA_CHENGXU/crc2/crc_p.vhd" 3 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "crc_and2.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file crc_and2.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 crc_and2-a " "Info: Found design unit 1: crc_and2-a" {  } { { "crc_and2.vhd" "" { Text "F:/FPGA_CHENGXU/crc2/crc_and2.vhd" 10 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 crc_and2 " "Info: Found entity 1: crc_and2" {  } { { "crc_and2.vhd" "" { Text "F:/FPGA_CHENGXU/crc2/crc_and2.vhd" 3 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "crc2 " "Info: Elaborating entity \"crc2\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "crc_p crc_p:inst6 " "Info: Elaborating entity \"crc_p\" for hierarchy \"crc_p:inst6\"" {  } { { "crc2.bdf" "inst6" { Schematic "F:/FPGA_CHENGXU/crc2/crc2.bdf" { { 160 1320 1496 256 "inst6" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "r4_out crc_p.vhd(19) " "Warning (10492): VHDL Process Statement warning at crc_p.vhd(19): signal \"r4_out\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "crc_p.vhd" "" { Text "F:/FPGA_CHENGXU/crc2/crc_p.vhd" 19 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "r4_out crc_p.vhd(23) " "Warning (10492): VHDL Process Statement warning at crc_p.vhd(23): signal \"r4_out\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "crc_p.vhd" "" { Text "F:/FPGA_CHENGXU/crc2/crc_p.vhd" 23 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0}