代码搜索：QDR SRAM

找到约 7,112 项符合「QDR SRAM」的源代码

代码结果 7,112
热门代码： main.c GPIO I2C SPI UART timer interrupt ADC PWM LED
www.eeworm.com/read/376227/9324271

ab1 xupsd.ab1

module xupsd pa7 PIN 21; lcd_cs PIN 66; f_cs PIN 67; pb5 PIN 72; pb4 PIN 73; pb3 PIN 74; tdo PIN 6; "TDO tdi PIN 7; "TDI vbaton PIN 9; "Standby-on indicator vstby PIN 15; "SRAM standby volta
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www.eeworm.com/read/376227/9324276

abl xupsd.abl

module xupsd pa7 PIN 21; lcd_cs PIN 66; f_cs PIN 67; pb5 PIN 72; pb4 PIN 73; pb3 PIN 74; tdo PIN 6; "TDO tdi PIN 7; "TDI vbaton PIN 9; "Standby-on indicator vstby PIN 15; "SRAM standby volta
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www.eeworm.com/read/376227/9324284

ab0 xupsd.ab0

module xupsd pa7 PIN 21; lcd_cs PIN 66; f_cs PIN 67; pb5 PIN 72; pb4 PIN 73; pb3 PIN 74; tdo PIN 6; "TDO tdi PIN 7; "TDI vbaton PIN 9; "Standby-on indicator vstby PIN 15; "SRAM standby volta
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www.eeworm.com/read/267307/6933312

hier_info scanwave.hier_info

|SCANWAVE RDAD MAX114:inst11.CLK CLK => BUS_1:inst5.CLK CLK => AD_SRAM:inst19.CLK CLK => CONV_SINGLE:inst22.CLK CLK => dram:inst.wrclock CLK => dram:inst.rdclock C
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www.eeworm.com/read/267307/6933359

hier_info test.hier_info

|TEST XFER AD_SRAM:inst2.CLK CLK => BUS_1:inst9.CLK CLK => dram:inst.wrclock CLK => dram:inst.rdclock CLK => FREDEVIDER8:78.CLKIN INTN
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www.eeworm.com/read/387872/7849860

dbg spi4_rx.dbg

.%scope file "G:\IXA_SDK_3.5\modify_c_hw3\spi4_rx.c" .%scope function ixp_buf_alloc _ixp_buf_alloc "G:\IXA_SDK_3.5\src\library\dataplane_library\microC\ixp_buf.c" 630 668 .%arg out_sram_addr 0 out_s
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www.eeworm.com/read/198527/7931237

cmd lnk.cmd

lab7.obj vectors.obj init.obj -o lab7.out -m lab7.map MEMORY { VECS: origin = 0h, length = 200h EPROM: origin = 200h, length = 0FFE00h SRAM: origin = 100000h, length = 8000h ADC: ori
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www.eeworm.com/read/153273/12044347

s sysinit.s

INCLUDE s3c4510.s RomBaseAddr EQU 0 RamBaseAddr EQU &100 RamEndAddr EQU &200 AREA text, CODE, READONLY SFR_BASE EQU 0x3ff ;0x3ff0000 SRAM_BASE EQU 0x3f8 ;0x3f80000 MemCfgPara
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www.eeworm.com/read/151112/12234718

s sysinit.s

INCLUDE s3c4510.s RomBaseAddr EQU 0 RamBaseAddr EQU &100 RamEndAddr EQU &200 AREA text, CODE, READONLY SFR_BASE EQU 0x3ff ;0x3ff0000 SRAM_BASE EQU 0x3f8 ;0x3f80000 MemCfgPara
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www.eeworm.com/read/116811/14952816

bak platform.inc.bak

IF :LNOT: :DEF: __plantforminc_s __plantforminc_s EQU 1 INCLUDE regClock.inc ; Flash timing values MSC0_28f128J3A_PM EQU 0x24F2 MSC0_28f128J3A_NB EQU 0x2BF0 ; SRAM timing valu
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