platform.inc.bak

嵌入式系统启动代码

    IF :LNOT: :DEF: __plantforminc_s
__plantforminc_s   EQU    1

  INCLUDE regClock.inc

; Flash timing values
MSC0_28f128J3A_PM	EQU		0x24F2
MSC0_28f128J3A_NB	EQU		0x2BF0

; SRAM timing values
MSC1_INIT			EQU		0x98B1
MSC2_INIT			EQU		0xF9F1

; pcmcia timing values
MECR_INIT			EQU    0x0
MCMEM0_INIT   		EQU    0x0
MCMEM1_INIT   		EQU    0x0
MCATT0_INIT   		EQU    0x0
MCATT1_INIT   		EQU    0x0
MCIO0_INIT    		EQU    0x0
MCIO1_INIT    		EQU    0x0

; SDRAM timing values
MDCNFG_SETTINGS   EQU    0x00001AC9 
MDMRS_SETTINGS    EQU    0x0
;MDREFR_SETTINGS   EQU    0x000BC018
;MDREFR_SETTINGS   EQU    0x0109C018
MDREFR_SETTINGS   EQU    0x010bc0BE

; synchronous static memory timing values
SXCNFG_SETTINGS   EQU    0x0



; platform gpio pin settings. 
; These value is used for start up. Only 
; 		GP1(GPIO_Reset)
; 		GP15, GP78, GP79, GP80, GP33 (nCS_1,nCS_2,nCS_3,nCS_4,nCS_5) 
; 		GP34, GP35, GP36, GP37, GP38, GP39, GP40, GP41 (FFUART pins)
; are set to alternate functions

PLATFORM_GPSRx        EQU     (0x00008000) 
PLATFORM_GPSRy        EQU     (0x00000002)
PLATFORM_GPSRz        EQU     (0x0001C000)

; In reset_handler we :
; 1. Write GPSR and GPCR
; 2. Write GPDR			Now the some GPIOs are output suce as nCSx. It will make bus confic. 
;						So we must set nCSx high before we set GPDR
; 3. Write GAFR


PLATFORM_GPCRx        EQU     (0x0)
PLATFORM_GPCRy        EQU     (0x0)
PLATFORM_GPCRz        EQU     (0x0)

PLATFORM_GPDRx        EQU     (0x09008000)    
PLATFORM_GPDRy        EQU     (0x00000002)
PLATFORM_GPDRz        EQU     (0x0001C000)

PLATFORM_GAFR0x        EQU     (0x80000000)
PLATFORM_GAFR1x        EQU     (0x0)
PLATFORM_GAFR0y        EQU     (0x00000000)
PLATFORM_GAFR1y        EQU     (0x0)
PLATFORM_GAFR0z        EQU     (0xA0000000)
PLATFORM_GAFR1z        EQU     (0x00000002)

; platform board level register settings. 

PLATREGS_PHYSICAL_BASE EQU     (0x08000000)

OFFSET_REG_PCR			  	EQU		(0x0)	;R/W 
OFFSET_REG_BCR				EQU		(0x4)	;R/W
OFFSET_REG_BSR				EQU		(0x8)	;R/O
OFFSET_REG_BIPR				EQU		(0xC)	;R/W
OFFSET_REG_BIMR				EQU		(0x10)	;R/W
OFFSET_REG_AXWR				EQU		(0x14)	;R/O
OFFSET_REG_AXLR				EQU		(0x18)	;R/O
OFFSET_REG_AYWR				EQU		(0x1C)	;R/O
OFFSET_REG_JSSR				EQU		(0x20)	;R/O
OFFSET_REG_PMR				EQU		(0x24)	;R/O
OFFSET_REG_PLWR				EQU		(0x28)	;R/O
OFFSET_REG_PRWR				EQU		(0x2C)	;R/O

REG_PCR_CF_ON				EQU		(BIT0);
REG_PCR_USB_HOST_ON			EQU		(BIT1);
REG_PCR_RS232_ON			EQU		(BIT2);
REG_PCR_SD_ON				EQU		(BIT3);
REG_PCR_ACC_ON				EQU		(BIT4);
REG_PCR_PEN_ON				EQU		(BIT5);
REG_PCR_LCD_ON				EQU		(BIT6);
REG_PCR_BACKLIGHT_ON		EQU		(BIT7);
REG_PCR_IRDA_ON				EQU		(BIT8);
REG_PCR_AUDIO_ON			EQU		(BIT9);
REG_PCR_DELAY_WAKEUP		EQU		(BIT10);
REG_PCR_PER_ON				EQU		(BIT14);
REG_PCR_PWR_OFF				EQU		(BIT15);

REG_BCR_FLASH_B0_WP			EQU		(BIT0)
REG_BCR_FLASH_B1_WP			EQU		(BIT1)
REG_BCR_CF_BUS_OPEN			EQU		(BIT2)
REG_BCR_CF_RESET			EQU		(BIT3)
REG_BCR_CF_CSEL				EQU		(BIT4)
REG_BCR_USB_BUS_OPEN		EQU		(BIT5)
REG_BCR_USB_NDP				EQU		(BIT6)
REG_BCR_USB_HC_RESET		EQU		(BIT7)
REG_BCR_USB_HC_WAKE			EQU		(BIT8)
REG_BCR_TS_CS				EQU		(BIT9)
REG_BCR_IR_MODE0			EQU		(BIT10)
REG_BCR_IR_MODE1			EQU		(BIT11)
REG_BCR_IR_FSEL				EQU		(BIT12)
REG_BCR_RED_LED				EQU		(BIT13)
REG_BCR_GREEN_LED			EQU		(BIT14)
REG_BCR_SYS_RESET			EQU		(BIT15)

REG_BSR_CF_IS5V				EQU		(BIT0)
REG_BSR_SD_WP				EQU		(BIT1)
REG_BSR_BOOT_FROM			EQU		(BIT2)
REG_BSR_USB_HC_SUSPEND		EQU		(BIT3)
REG_BSR_TS_READY			EQU		(BIT4)
REG_BSR_CF_VS2				EQU		(BIT5)
REG_BSR_USB_DC_INSERT		EQU		(BIT7)
REG_BSR_USB_HC1_INSERT		EQU		(BIT8)
REG_BSR_USB_HC2_INSERT		EQU		(BIT9)
REG_BSR_USB_HC1_OC			EQU		(BIT10)
REG_BSR_USB_HC2_OC			EQU		(BIT11)
REG_BSR_BATT_CHARGING		EQU		(BIT12)
REG_BSR_RS232_INSERT		EQU		(BIT13)
REG_BSR_CF_CARD_INSERT		EQU		(BIT14)
REG_BSR_SD_INSERT			EQU		(BIT15)

REG_BIPR_CF_DETECT_IRQ		EQU		(BIT0)
REG_BIPR_CF_IRQ 			EQU		(BIT1)
REG_BIPR_USB_B_DETECT_IRQ	EQU		(BIT2)
REG_BIPR_USB_HC1_DETECT_IRQ	EQU		(BIT3)
REG_BIPR_USB_HC2_DETECT_IRQ	EQU		(BIT4)
REG_BIPR_USB_HC1_OC_IRQ		EQU		(BIT5)
REG_BIPR_USB_HC2_OC_IRQ		EQU		(BIT6)
REG_BIPR_USB_HC_IRQ 		EQU		(BIT7)
REG_BIPR_RS232_DETECT_IRQ	EQU		(BIT8)
REG_BIPR_SD_DETECT_IRQ		EQU		(BIT9)
REG_BIPR_ACC_IRQ 			EQU		(BIT10)
REG_BIPR_JOYSTICK_IRQ 		EQU		(BIT11)
REG_BIPR_PEN_MODE_IRQ 		EQU		(BIT12)
REG_BIPR_PEN_POSITION_IRQ	EQU		(BIT13)
REG_BIPR_BATT_CHARGED_IRQ	EQU		(BIT14)
REG_BIPR_TOUCH_IRQ 			EQU		(BIT15)

REG_BIMR_CF_DETECT_IRQ		EQU		(BIT0)
REG_BIMR_CF_IRQ 			EQU		(BIT1)
REG_BIMR_USB_B_DETECT_IRQ	EQU		(BIT2)
REG_BIMR_USB_HC1_DETECT_IRQ	EQU		(BIT3)
REG_BIMR_USB_HC2_DETECT_IRQ	EQU		(BIT4)
REG_BIMR_USB_HC1_OC_IRQ		EQU		(BIT5)
REG_BIMR_USB_HC2_OC_IRQ		EQU		(BIT6)
REG_BIMR_USB_HC_IRQ 		EQU		(BIT7)
REG_BIMR_RS232_DETECT_IRQ	EQU		(BIT8)
REG_BIMR_SD_DETECT_IRQ		EQU		(BIT9)
REG_BIMR_ACC_IRQ 			EQU		(BIT10)
REG_BIMR_JOYSTICK_IRQ 		EQU		(BIT11)
REG_BIMR_PEN_MODE_IRQ 		EQU		(BIT12)
REG_BIMR_PEN_POSITION_IRQ	EQU		(BIT13)
REG_BIMR_BATT_CHARGED_IRQ	EQU		(BIT14)
REG_BIMR_TOUCH_IRQ 			EQU		(BIT15)

REG_AXWR					EQU		(0x03FF)
REG_AXLR					EQU		(0x0000)
REG_AYWR					EQU		(0x03FF)

REG_JSSR_LEFT				EQU		(BIT0)
REG_JSSR_RIGHT				EQU		(BIT1)
REG_JSSR_TOP				EQU		(BIT2)
REG_JSSR_BOTTOM				EQU		(BIT3)
REG_JSSR_CENTER				EQU		(BIT4)
REG_JSSR_SBT0				EQU		(BIT5)
REG_JSSR_SBT1				EQU		(BIT6)
REG_JSSR_GPRBT				EQU		(BIT7)

REG_PMR						EQU		(0x000F)
REG_PLWR					EQU		(0x07FF)
REG_PRWR					EQU		(0x07FF)


; for 100 mhz sdram
PLATFORM_MEMORY     		EQU     CCCR_L27

CORE_CLK_100MHZ       		EQU     (PLATFORM_MEMORY :OR: CCCR_M1 :OR: CCCR_N10)     
CORE_CLK_133MHZ       		EQU     (CCCR_L36 :OR: CCCR_M1 :OR: CCCR_N10)     
CORE_CLK_200MHZ       		EQU     (PLATFORM_MEMORY :OR: CCCR_M2 :OR: CCCR_N10)     
CORE_CLK_400MHZ       		EQU     (PLATFORM_MEMORY :OR: CCCR_M4 :OR: CCCR_N10)     

CORE_CLK_DEFAULT      		EQU     (CORE_CLK_200MHZ)
CORE_CLK_ALT          		EQU     (CORE_CLK_100MHZ)


	ENDIF

        END