spi4_rx.dbg

ixp2400的一个小程序

.%scope file "G:\IXA_SDK_3.5\modify_c_hw3\spi4_rx.c"
.%scope function ixp_buf_alloc _ixp_buf_alloc "G:\IXA_SDK_3.5\src\library\dataplane_library\microC\ixp_buf.c" 630 668
.%arg out_sram_addr 0 out_sram_addr_722_V$402
.%arg POOL_ID 5 POOL_ID_722_V$403
.%arg d_base 4 d_base_722_V$404
.%arg d_size 4 d_size_722_V$405
.%arg s_base 4 s_base_722_V$406
.%arg s_size 4 s_size_722_V$407
.%arg REQ_SIG 6 REQ_SIG_722_V$408
.%arg wakeup_sigs 4 wakeup_sigs_722_V$409
.%arg Q_OPTION 4 Q_OPTION_722_V$40a
.%var _BUF_ALLOC_CHNL_NUM 4 _BUF_ALLOC_CHNL_NUM_722 LIX
.%var sram_qa_addr 4 sram_qa_addr_722 LIX
.%scope end
.%var dlBufHandle 1 _dlBufHandle SEX
.%var dlNextBlock 7 _dlNextBlock SEX
.%var dlMeta 8 _dlMeta SEX
.%scope function ixp_buf_free _ixp_buf_free "G:\IXA_SDK_3.5\src\library\dataplane_library\microC\ixp_buf.c" 703 732
.%arg in_sram_addr 1 in_sram_addr_724_V$40d
.%arg POOL_ID 5 POOL_ID_724_V$415
.%arg d_base 4 d_base_724_V$416
.%arg d_size 4 d_size_724_V$417
.%arg s_base 4 s_base_724_V$418
.%arg s_size 4 s_size_724_V$419
.%var _BUF_FREE_CHNL_NUM 4 _BUF_FREE_CHNL_NUM_724 LIX
.%var _sram_addr 4 _sram_addr_724 LIX
.%scope end
.%scope function Dl_BufAlloc _Dl_BufAlloc "G:\IXA_SDK_3.5\src\library\microblocks_library\microc\dl_buf.c" 77 91
.%arg bufHandle 12 bufHandle_733_V$41c
.%arg freeList 5 freeList_733_V$41d
.%arg dBase 4 dBase_733_V$41e
.%arg dSize 4 dSize_733_V$41f
.%arg sBase 4 sBase_733_V$420
.%arg sSize 4 sSize_733_V$421
.%arg reqSig 6 reqSig_733_V$422
.%arg sigAction 4 sigAction_733_V$423
.%arg Q_OPTION 4 Q_OPTION_733_V$424
.%scope end
.%scope function Dl_BufFree _Dl_BufFree "G:\IXA_SDK_3.5\src\library\microblocks_library\microc\dl_buf.c" 115 125
.%arg bufHandle 1 bufHandle_734_V$425
.%arg freeList 5 freeList_734_V$42d
.%arg dBase 4 dBase_734_V$42e
.%arg dSize 4 dSize_734_V$42f
.%arg sBase 4 sBase_734_V$430
.%arg sSize 4 sSize_734_V$431
.%scope end
.%scope function Dl_BufGetData _Dl_BufGetData "G:\IXA_SDK_3.5\src\library\microblocks_library\microc\dl_buf.c" 191 208
.%arg bufHandle 1 bufHandle_736_V$432
.%var sdramOffset 4 sdramOffset_736 LIX
.%scope end
.%scope function Dl_BufDrop _Dl_BufDrop "G:\IXA_SDK_3.5\src\library\microblocks_library\microc\dl_buf.c" 263 266
.%arg bufHandle 1 bufHandle_738_V$43c
.%scope end
.%scope function _spi4_rx_free_rbuf __spi4_rx_free_rbuf "G:\IXA_SDK_3.5\modify_c_hw3\spi4_rx.c" 78 87
.%arg in_elem 4 in_elem_749_V$444
.%var val_and_addr 13 val_and_addr_749 LIX
.%scope end
.%scope function _spi4_rx_get_mpacket __spi4_rx_get_mpacket "G:\IXA_SDK_3.5\modify_c_hw3\spi4_rx.c" 181 226
.%var rx_complete_sig 7 rx_complete_sig_751 LIX
.%var rsw 15 rsw_751 LIR
.%var rx_tfl 19 rx_tfl_751 LIX
.%var rx_tfl_addr_and_val 13 rx_tfl_addr_and_val_751 LIX
.%scope end
.%scope function _spi4_rx_move_rbuf_to_dram __spi4_rx_move_rbuf_to_dram "G:\IXA_SDK_3.5\modify_c_hw3\spi4_rx.c" 256 286
.%arg in_rbuf_elem 4 in_rbuf_elem_754_V$474
.%arg in_dram_addr 21 in_dram_addr_754_V$475
.%arg in_size 4 in_size_754_V$476
.%arg in_dram_sig 22 in_dram_sig_754_V$477
.%var indir 24 indir_754 LIX
.%var rbuf_addr 4 rbuf_addr_754 LIX
.%scope end
.%scope function spi4_rx_init _spi4_rx_init "G:\IXA_SDK_3.5\modify_c_hw3\spi4_rx.c" 109 159
.%var addr 13 addr_750 LIX
.%var rx_ctl 4 rx_ctl_750 LIW
.%var msf_rx_ctl_sig 7 msf_rx_ctl_sig_750 LIX
.%scope end
.%scope function spi4_rx _spi4_rx "G:\IXA_SDK_3.5\modify_c_hw3\spi4_rx.c" 316 409
.%var cur_mpacket_addr 27 cur_mpacket_addr_755 LIX
.%var alloc_handle 1 alloc_handle_755 LIR
.%var rsw 15 rsw_755 LIX
.%var rbuf_to_dram_sig 23 rbuf_to_dram_sig_755 LIX
.%var buf_alloc_sig 7 buf_alloc_sig_755 LIX
.%scope end
.%type P2 1
.%type S4 {
__unnamed 0 2;
}
.%type S4 {
__unnamed 0 3;
value 0 4;
}
.%type S4 {
eop 0:31:1 4;
sop 0:30:1 4;
seg_count 0:24:6 4;
lw_offset 0:0:24 4;
}
.%type U4
.%type E4 {
POOL0 0;
POOL1 1;
POOL2 2;
POOL3 3;
POOL4 4;
POOL5 5;
POOL6 6;
POOL7 7;
}
.%type P2 7
.%type I4
.%type S32 {
__unnamed 0 9;
value 0 11;
}
.%type S32 {
bufferNext 0 1;
bufferSize 4 10;
offset 6 10;
packetSize 8:16:16 4;
freeListId 8:12:4 4;
rxStat 8:8:4 4;
headerType 8:0:8 4;
inputPort 12 10;
outputPort 14 10;
nextHopId 16:16:16 4;
fabricPort 16:8:8 4;
reserved 16:4:4 4;
nhidType 16:0:4 4;
colorId 20:28:4 4;
reserved1 20:24:4 4;
flowId 20:0:24 4;
classId 24 10;
reserved2 26 10;
packetNext 28 4;
}
.%type U2
.%type A32 4
.%type P2 1
.%type P2 14
.%type U4
.%type S8 s_spi4_rsw{
w1 0 16;
w2 4 18;
}
.%type S4 {
parts 0 17;
whole 0 4;
}
.%type S4 {
rprot 0:31:1 4;
element 0:24:7 4;
byte_count 0:16:8 4;
sop 0:15:1 4;
eop 0:14:1 4;
err 0:13:1 4;
len_err 0:12:1 4;
par_err 0:11:1 4;
abort_err 0:10:1 4;
null 0:9:1 4;
type 0:8:1 4;
addr 0:0:8 4;
}
.%type S4 {
whole 0 4;
}
.%type S4 {
parts 0 20;
whole 0 4;
}
.%type S4 {
res 0:16:16 4;
sig_no 0:12:4 4;
me_no 0:7:5 4;
thd 0:4:3 4;
xfer_reg 0:0:4 4;
}
.%type P3 14
.%type P2 23
.%type S8 {
even 0 7;
odd 4 7;
}
.%type S4 dram_rbuf_tbuf_ind_t{
__unnamed 0 25;
}
.%type S4 {
__unnamed 0 26;
value 0 4;
}
.%type S4 {
ov_ueng_addr 0:31:1 4;
ueng_addr 0:26:5 4;
ov_ref_count 0:25:1 4;
ref_count 0:21:4 4;
reserved 0:19:2 4;
buf_addr 0:5:14 4;
ov_buf_addr 0:4:1 4;
ov_ctx 0:3:1 4;
ctx 0:0:3 4;
}
.%type P3 28
.%type U1