代码搜索:Process

找到约 10,000 项符合「Process」的源代码

代码结果 10,000
www.eeworm.com/read/442048/7660871

vhd fenwei.vhd

library ieee; use ieee.std_logic_1164.all; entity fenwei is port (innum:in integer range 0 to 25; shiwei,gewei:out integer range 0 to 9); end; architecture b_fenwei of fenwei is begin p
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vhd counter.vhd

LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY counter IS PORT (Hold, Reset, Clk : IN STD_LOGIC; Num : Buffer Integer Range 0 To 49 ); END counter; ARCHITECTURE counter_a
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h convertdialog.ui.h

void ConvertDialog::init() { process = 0; QStringList imageFormats = QImage::outputFormatList(); targetFormatComboBox->insertStringList(imageFormats); fileFilters = tr("Images") + " (*
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rpt crc2.map.rpt

Analysis & Synthesis report for crc2 Wed Oct 15 01:40:11 2008 Quartus II Version 7.2 Build 151 09/26/2007 SJ Full Version --------------------- ; Table of Contents ; ---------------------
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bak fenpin.vhd.bak

LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY fenpin IS PORT ( clk : IN STD_LOGIC; start : IN STD_LOGIC; clkout : OUT STD_LOGIC ); END fenpin; ARCHITECTURE a OF fenpin IS
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bak fp2.vhd.bak

LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY fp2 IS PORT ( clk : IN STD_LOGIC; clkout : OUT STD_LOGIC ); END fp2; ARCHITECTURE a OF fp2 IS signal j:integer range 0 to 39999:=0;
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vhd fenpin.vhd

LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY fenpin IS PORT ( clk : IN STD_LOGIC; start : IN STD_LOGIC; clkout : OUT STD_LOGIC ); END fenpin; ARCHITECTURE a OF fenpin IS
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vhd fp2.vhd

LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY fp2 IS PORT ( clk : IN STD_LOGIC; clkout : OUT STD_LOGIC ); END fp2; ARCHITECTURE a OF fp2 IS signal j:integer range 0 to 39999:=0;
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txt text.txt

Sel 1 Sel Sel Sel Sel Sel Sel 255 90Sel 1677721
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cpp p14.cpp

#include #include #include void main() { ofstream outFile ("my.out"); if (! outFile ) { cout