fp2.vhd.bak

基于FPGA的秒表设计基于FPGA的秒表设计基于FPGA的秒表设计

LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY fp2 IS
	PORT
	(
		clk : IN STD_LOGIC;
	 clkout : OUT STD_LOGIC
	);
END fp2;

ARCHITECTURE a OF fp2 IS
signal j:integer range 0 to 39999:=0;
signal clk1:STD_LOGIC:='0';
BEGIN
process(clk)
	begin
		if (clk 'event and clk='1') then
			if j=39999 then
			 j<=0;
			 clk1<='1';
			else
			 j<=j+1;
			 clk1<='0';
			end if;
		end if;
	end process;
clkout<=clk1;
END a;