fenpin.vhd

基于FPGA的秒表设计基于FPGA的秒表设计基于FPGA的秒表设计

LIBRARY ieee;
USE ieee.std_logic_1164.all;

ENTITY fenpin IS
	PORT
	(
		clk : IN STD_LOGIC;
	  start : IN STD_LOGIC;
	 clkout : OUT STD_LOGIC
	);
END fenpin;

ARCHITECTURE a OF fenpin IS
signal j:integer range 0 to 399999:=0;
signal clk1:STD_LOGIC:='0';
BEGIN
process(clk)
	begin
	if (start='1') then
	 if (clk 'event and clk='1') then
	  if j=399999 then
		 j<=0;
		 clk1<='1';
	  else
		 j<=j+1;
		 clk1<='0';
	  end if;
	 end if;
	 else clk1<='0';
    end if;
end process;
clkout<=clk1;
END a;