counter.vhd

来自「用VHDL做的交通灯设计」· VHDL 代码 · 共 27 行

LIBRARY ieee;
USE ieee.std_logic_1164.all;

ENTITY counter IS
	PORT (Hold, Reset, Clk 	: IN 	  STD_LOGIC;			
		  Num 				: Buffer  Integer Range 0 To 49 );
END counter;

ARCHITECTURE counter_architecture OF counter IS
BEGIN
	PROCESS (reset, clk, hold)
	BEGIN
		If   (reset='1') 	Then	num <= 0;	-- 系统启动，开始计数
		Else 
	   		If  ( rising_edge(clk) )   Then
		  		If    ( hold='1') Then 
					num <= num;				-- 出现特殊情况，暂停计数
		  		Elsif ( num<49 )  Then
			 		num <= num+1;			-- 每个时钟周期，计数加1
		  		Elsif ( num=49 )  Then
			 		num <= 0;				-- 计数规零，重新计数
		  		End If;
	 		End If;
	 	End If; 
	END PROCESS;
END counter_architecture;