代码搜索：Process
找到约 10,000 项符合「Process」的源代码
代码结果 10,000
www.eeworm.com/read/460213/7255639
vhd fredivn.vhd
--evev frequency division
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity fredivn is
GENERIC (N:integer:=8);
port (clk:in std
www.eeworm.com/read/459739/7265334
plg gsm.plg
礦ision3 Build Log
Project:
F:\毕业设计\毕业设计资料\用51单片机开发的GSM报警程序\gsm\gsm.uv2
Project File Date: 04/10/2009
Output:
Build target 'Target 1'
assembli
www.eeworm.com/read/459533/7274102
vhd clkgenbaojing.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY CLKGENBAOJING IS
PORT (
CLK:IN STD_LOGIC; --12 MHz信号输入
ENA:IN STD_LOGIC;
DONE:IN STD_LOGIC;
NEWCLK:OUT STD_LOGIC );--1 Hz计
www.eeworm.com/read/459533/7274124
vhd clkgen.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY CLKGEN IS
PORT (
CLK:IN STD_LOGIC; --12 MHz信号输入
NEWCLK:OUT STD_LOGIC );--1 Hz计时时钟信号输出
END CLKGEN;
ARCHITECTURE ART OF CLKG
www.eeworm.com/read/459533/7274135
vhd gen.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY GEN IS
PORT (
CLK:IN STD_LOGIC; --12 MHz信号输入
NEWCLK:OUT STD_LOGIC );--1 Hz计时时钟信号输出
END GEN;
ARCHITECTURE ART OF GEN IS
SI
www.eeworm.com/read/459468/7275008
plg 遥控.plg
Build target 'Target 1'
compiling main.c...
linking...
*** WARNING L16: UNCALLED SEGMENT, IGNORED FOR OVERLAY PROCESS
SEGMENT: ?PR?DELAY?MAIN
creating hex file from "遥控"...
"遥控" - 0 Error(s), 1 W
www.eeworm.com/read/459461/7275195
vhd comparador.vhd
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity COMPARADOR is
generic (ANCHO: integer := 8;
EOS : integer :=
www.eeworm.com/read/459395/7276154
java pythonutil.java
/**
*
*/
package com.coretek.tools.j2me.coral.python;
import java.io.ByteArrayOutputStream;
import java.io.DataOutputStream;
import java.io.File;
import java.io.IOException;
import java.i
www.eeworm.com/read/459288/7277835
c election.c
/*.....................................................
//Program For Implementing Election Algorithm
....................................................*/
#include
#include
www.eeworm.com/read/459160/7279590
vhd div9.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity div9 is
port(clk1:in std_logic;
reset:in std_logic;
C_EN