clkgenbaojing.vhd

来自「微波炉控制器的设计」· VHDL 代码 · 共 44 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY CLKGENBAOJING IS
   PORT (
		CLK:IN STD_LOGIC; --12 MHz信号输入
		    ENA:IN STD_LOGIC; 
		DONE:IN STD_LOGIC; 
     NEWCLK:OUT STD_LOGIC  );--1 Hz计时时钟信号输出
END CLKGENBAOJING;


ARCHITECTURE ART OF  CLKGENBAOJING IS
SIGNAL CNTER:INTEGER RANGE 0 TO 10#500#;
SIGNAL FULL:STD_LOGIC;	--十进制计数预制数
BEGIN
PROCESS(CLK)   								--分频计数器，由3 MHz时钟产生100 Hz信号
BEGIN 
IF CLK'EVENT AND CLK='1' THEN

IF CNTER=10#500# THEN CNTER<=0;		--3 MHz信号变为100 Hz，计数常数为30 000
         ELSE CNTER<=CNTER+1;
         END IF;
     
END IF;
END PROCESS;
PROCESS(CNTER)         						--计数溢出信号控制
BEGIN    
     IF CNTER=10#500# THEN FULL<='1';
     ELSE FULL<='0';
     END IF;
     END PROCESS;
PROCESS(FULL,ENA,DONE)     
VARIABLE CNT2:STD_LOGIC;    						--计数溢出信号控制
BEGIN
    IF (ENA AND DONE)='0' THEN NEWCLK<='0';
    ELSIF  FULL'EVENT AND FULL='1' THEN
         CNT2:= NOT CNT2;     
     IF CNT2='1' THEN NEWCLK<='1';
         ELSE NEWCLK<='0';
     END IF;END IF;
     END PROCESS;
END ART;