div9.vhd

来自「分别用分频比交错法及累加器分频法完成非整数分频器设计。」· VHDL 代码 · 共 30 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity div9 is
port(clk1:in std_logic;      
         reset:in std_logic;
         C_ENB1:out std_logic;
         cout1:out std_logic);
end div9;
architecture behave of div9 is
signal cnt:std_logic_vector(3 downto 0);
begin
process(clk1,reset)
begin
if(reset='1')then
  cnt<="0000";
  cout1<='0';
elsif(clk1'event and clk1='1')then
 if(cnt<8)then
   cnt<=cnt+"0001";
  else
  cnt<="0000";
 end if;
  cout1<=cnt(2);
  C_ENB1<=cnt(2) and cnt(1) and cnt(0);
end if;
end process;

end;