代码搜索：Numeric
找到约 7,754 项符合「Numeric」的源代码
代码结果 7,754
www.eeworm.com/read/140727/5782456
cc sigm_02.cc
// file: $isip/class/numeric/Sigmoid/sigm_02.cc
// version: $Id: sigm_02.cc,v 1.7 2001/11/13 15:30:23 gao Exp $
//
// isip include files
//
#include "Sigmoid.h"
#include
#include
www.eeworm.com/read/120487/6073280
h pgtypes_error.h
#define PGTYPES_NUM_OVERFLOW 301
#define PGTYPES_NUM_BAD_NUMERIC 302
#define PGTYPES_NUM_DIVIDE_ZERO 303
#define PGTYPES_DATE_BAD_DATE 310
#define PGTYPES_DATE_ERR_EARGS 311
#define PGTYPES_DATE
www.eeworm.com/read/476613/6756839
txt cpu和运算器级联.txt
Library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_unsigned.all;
use IEEE.NUMERIC_STD.all;
use IEEE.STD_LOGIC_arith.all;
Entity Reg is
port(
--Input port
Data : IN STD_LOGI
www.eeworm.com/read/263246/11370109
vhd gen_10ms.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
USE ieee.numeric_std.all;
entity GEN_10MS is
port(
CLK : in std_logic; --4096 Hz
SET_ZERO : in std_logic;
ENABLE_10MS : ou
www.eeworm.com/read/262569/11399730
bak addsubtractor.vhd.bak
Library IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.std_logic_unsigned.all;
USE IEEE.numeric_std.all;
USE IEEE.std_logic_arith.all;
Entity addsubtractor is
generic (size: integer:=4);
Port (in1
www.eeworm.com/read/262569/11399821
vhd addsubtractor.vhd
Library IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.std_logic_unsigned.all;
USE IEEE.numeric_std.all;
USE IEEE.std_logic_arith.all;
Entity addsubtractor is
generic (size: integer:=4);
Port (in1
www.eeworm.com/read/403922/11502723
html function.oci-fetch-row.html
Returns the next row from the result data as a numeric array
www.eeworm.com/read/403922/11503704
html internals2.counter.function.counter-create.html
Creates a counter which maintains a single numeric value.
www.eeworm.com/read/341658/12074383
vhd q_reg.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library basic;
use basic.mnemonics.all;
use basic.regs_pkg.all;
entity q_reg is port(
clk,rst:in std_logic;
www.eeworm.com/read/341658/12074387
vhd am2901.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library basic;
use basic.am2901_comps.all;
entity am2901 is port(
clk,rst:in std_logic;
a,b:in unsigned(3 downto