cpu和运算器级联.txt

本人主要是介绍CPU和运算器级联的程序

Library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_unsigned.all;
use IEEE.NUMERIC_STD.all;
use IEEE.STD_LOGIC_arith.all;

Entity Reg is
	port(
			--Input port
			Data	: IN STD_LOGIC_VECTOR(7 DOWNTO 0);
			CLK		: IN STD_LOGIC;
			Reset	: IN STD_LOGIC;
			M1,M0	: IN STD_LOGIC;
			RA1,RA0	: IN STD_LOGIC;
			WR,RD	: IN STD_LOGIC;
			ALE		: IN STD_LOGIC;
			--Output port
			Out0	: OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
			Out1	: OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
		);
End Entity Reg;
Architecture behav of Reg is
	signal CR	: STD_LOGIC_VECTOR(3 DOWNTO 0);
	signal M	: STD_LOGIC_VECTOR(1 DOWNTO 0);
	signal Dout	: STD_LOGIC_VECTOR(7 DOWNTO 0);--LED for Register
begin
	process(CLK,Reset,M1,M0,WR,RD,RA1,RA0,ALE)
		variable PC	: STD_LOGIC_VECTOR(15 DOWNTO 0);
		variable R0,R1,R2,R3 : STD_LOGIC_VECTOR(7 DOWNTO 0);
	begin
		M <= M1 & M0;
		CR <= RA1 & RA0 & WR & RD;

		------------------process PC------------------------
		if(CLK'Event and CLK='0') then
			if(Reset='1') then
				case M is
					when "00" => PC(7  DOWNTO 0) := Data;--set PCL
					when "01" => PC(15 DOWNTO 8) := Data;--set PCH
					when "10" => PC := PC + 1;			--PC++
					when "11" => PC := PC - 1;			--PC--
				end case;
			else
				PC := "0000000000000000";	--reset PC
			end if;
				
		-----------------process register-------------------
			case CR is
				when "0001" => R0 := Data;	--write R0
				when "0010" => Dout <= R0;	--read  R0
				
				when "0101" => R1 := Data;	--write R1
				when "0110" => Dout <= R1;	--read  R1
				
				when "1001" => R2 := Data;	--write R2
				when "1010" => Dout <= R2;	--read  R2
				
				when "1101" => R3 := Data;	--write R3
				when "1110" => Dout <= R3;	--read  R3
				
				when others => NULL;
			end case;
		end if;

		------------------process output--------------------
		if(ALE='0') then			
			Out0 <= PC(7  DOWNTO 0);	--output PC
			Out1 <= PC(15 DOWNTO 8);
		else
			Out0 <= Dout;				--output register
			Out1 <= PC(15 DOWNTO 8);	--output PCH
		end if;
	end process;
end Architecture behav;