addsubtractor.vhd.bak

vhdl 语言程序设计

Library IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.std_logic_unsigned.all;
USE IEEE.numeric_std.all;
USE IEEE.std_logic_arith.all;

Entity addsubtractor is 
  generic (size: integer:=4);
  Port (in1, in2: in std_logic_vector ( size-1 downto 0);
        ctrl:     in std_logic_vector ( 1 downto 0);
        sum:      out std_logic_vector ( size-1 downto 0);
        cout:     out std_logic);
End addsubtractor;

Architecture behavior of addsubtractor is 
  Begin 
      Process (in1,in2) 
          variable carry: std_logic; 
          variable sum1: std_logic_vector ( size-1 downto 0);
          variable notin2: std_logic_vector (size-1 downto 0);
        Begin  
          if ctrl="00" then 
            carry := '0';
             for i in 0 to size-1 loop
              sum1(i):= (in1(i) xor in2(i)) xor carry;
              carry := (in1(i) and in2(i)) or ( carry and ( in1(i) and in2(i)));
             end loop;
              sum<= sum1;
              cout<=carry;
            
            elsif ctrl="01" then 
              carry:='0';
              notin2:=1+(not in2);
               for i in 0 to size-1 loop
                sum1(i) :=  in1(i) xor notin2(i) xor carry; 
                carry := (in1(i) and notin2(i)) or ( carry and ( in1(i) and notin2(i)));
               end loop;
               sum<=sum1;
               cout<=carry;
             else
            end if;
    End process;
  End behavior;