gen_10ms.vhd

vhdl语言编写的一个秒表源码

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
USE ieee.numeric_std.all;


entity GEN_10MS is
  port(
    CLK           : in std_logic;   --4096 Hz
    SET_ZERO      : in std_logic;
    ENABLE_10MS   : out std_logic
  );
end GEN_10MS ;

architecture BEHAVIORAL_GEN_10MS of GEN_10MS is
  signal REG_OUT : std_logic_vector(5 downto 0);
  signal ADD_OUT : std_logic_vector(5 downto 0);
  signal ENABLE_OUT : std_logic;
  signal INCR    : std_logic_vector(5 downto 0);
begin

  INCR    <= "000001";
  
  p_reg: process(CLK)
  begin
   if CLK'event and CLK='1' then
     if SET_ZERO = '1' or ENABLE_OUT = '1' then
       REG_OUT <= (Others => '0');
     else
       REG_OUT <= ADD_OUT;
     end if;
   end if;
  end process;

  ADD_OUT <= std_logic_vector(unsigned(REG_OUT) + unsigned(INCR));

  ENABLE_OUT <= '1' when ADD_OUT = "101001" else '0';
  ENABLE_10MS <= ENABLE_OUT;

end BEHAVIORAL_GEN_10MS;