代码搜索：Memory
找到约 10,000 项符合「Memory」的源代码
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ngd visit_memory.ngd
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par visit_memory.par
Release 6.2i Par G.28
Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved.
song:: Sun Nov 11 22:55:12 2007
C:/Xilinx/bin/nt/par.exe -w -intstyle ise -ol std -t 1 visit_memory_map.ncd
visit_
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vhdl visit_memory.vhdl
library ieee;
library UNISIM;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use UNISIM.VComponents.all;
entity visit_memory is
port(
PCload: in
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vhw memory_wave.vhw
-- C:\XILINX\BIN\MYCPU16
-- VHDL Test Bench created by
-- HDL Bencher 6.1i
-- Thu Nov 15 13:55:08 2007
--
-- Notes:
-- 1) This testbench has been automatically generated from
-- your Test Be
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fdo memory_wave.fdo
## NOTE: Do not edit this file.
## Autogenerated by ProjNav (creatfdo.tcl) on Thu Nov 15 13:55:08 中国标准时间 2007
##
vlib work
vcom -93 -explicit memory.vhdl
vcom -93 -explicit memory_wave.vhw
vs
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pcf visit_memory.pcf
SCHEMATIC START ;
// created by map version G.28 on Sun Nov 11 22:55:11 2007
SCHEMATIC END ;
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xst visit_memory.xst
set -tmpdir __projnav
set -xsthdpdir ./xst
run
-ifn visit_memory.prj
-ifmt mixed
-ofn visit_memory
-ofmt NGC
-p xcv200-4-pq240
-top visit_memory
-opt_mode Speed
-opt_level 1
-iuc NO
-lso v
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bit visit_memory.bit
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