visit_memory.par

16位cpu设计VHDL源码

Release 6.2i Par G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.

song::  Sun Nov 11 22:55:12 2007


C:/Xilinx/bin/nt/par.exe -w -intstyle ise -ol std -t 1 visit_memory_map.ncd
visit_memory.ncd visit_memory.pcf 


Constraints file: visit_memory.pcf

Loading device database for application Par from file "visit_memory_map.ncd".
   "visit_memory" is an NCD, version 2.38, device xcv200, package pq240, speed
-4
Loading device for application Par from file 'v200.nph' in environment
C:/Xilinx.
Device speed data version:  FINAL 1.123 2003-12-13.


Device utilization summary:

   Number of External GCLKIOBs         1 out of 4      25%
   Number of External IOBs           103 out of 166    62%
      Number of LOCed External IOBs    0 out of 103     0%

   Number of SLICEs                   14 out of 2352    1%

   Number of GCLKs                     1 out of 4      25%



Overall effort level (-ol):   Standard (set by user)
Placer effort level (-pl):    Standard (set by user)
Placer cost table entry (-t): 1
Router effort level (-rl):    Standard (set by user)


Phase 1.1
Phase 1.1 (Checksum:98985b) REAL time: 0 secs 

Phase 2.23
Phase 2.23 (Checksum:1312cfe) REAL time: 0 secs 

Phase 3.3
Phase 3.3 (Checksum:1c9c37d) REAL time: 0 secs 

Phase 4.5
Phase 4.5 (Checksum:26259fc) REAL time: 0 secs 

Phase 5.8
.
Phase 5.8 (Checksum:9c7713) REAL time: 0 secs 

Phase 6.5
Phase 6.5 (Checksum:39386fa) REAL time: 0 secs 

Phase 7.18
Phase 7.18 (Checksum:42c1d79) REAL time: 0 secs 

Writing design to file visit_memory.ncd.

Total REAL time to Placer completion: 0 secs 
Total CPU time to Placer completion: 0 secs 


Phase 1: 182 unrouted;       REAL time: 0 secs 

Phase 2: 162 unrouted;       REAL time: 0 secs 

Phase 3: 21 unrouted;       REAL time: 0 secs 

Phase 4: 0 unrouted;       REAL time: 0 secs 

Total REAL time to Router completion: 0 secs 
Total CPU time to Router completion: 0 secs 

Generating "par" statistics.

**************************
Generating Clock Report
**************************

+----------------------------+----------+--------+------------+-------------+
|         Clock Net          | Resource | Fanout |Net Skew(ns)|Max Delay(ns)|
+----------------------------+----------+--------+------------+-------------+
|      PCload_BUFGP          |  Global  |   40   |  0.076     |  0.615      |
+----------------------------+----------+--------+------------+-------------+


   The Delay Summary Report

   The SCORE FOR THIS DESIGN is: 404


The NUMBER OF SIGNALS NOT COMPLETELY ROUTED for this design is: 0

   The AVERAGE CONNECTION DELAY for this design is:        2.810
   The MAXIMUM PIN DELAY IS:                              11.276
   The AVERAGE CONNECTION DELAY on the 10 WORST NETS is:   6.160

   Listing Pin Delays by value: (nsec)

    d < 2.00   < d < 4.00  < d < 6.00  < d < 8.00  < d < 12.00  d >= 12.00
   ---------   ---------   ---------   ---------   ---------   ---------
          75          66          32           4           5           0

Generating Pad Report.

All signals are completely routed.

Total REAL time to PAR completion: 0 secs 
Total CPU time to PAR completion: 1 secs 

Peak Memory Usage:  54 MB

Placement: Completed - No errors found.
Routing: Completed - No errors found.

Writing design to file visit_memory.ncd.


PAR done.