memory_wave.vhw

16位cpu设计VHDL源码

-- C:\XILINX\BIN\MYCPU16
-- VHDL Test Bench created by
-- HDL Bencher 6.1i
-- Thu Nov 15 13:55:08 2007
-- 
-- Notes:
-- 1) This testbench has been automatically generated from
--   your Test Bench Waveform
-- 2) To use this as a user modifiable testbench do the following:
--   - Save it as a file with a .vhd extension (i.e. File->Save As...)
--   - Add it to your project as a testbench source (i.e. Project->Add Source...)
-- 

LIBRARY IEEE;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_TEXTIO.ALL;
USE STD.TEXTIO.ALL;

ENTITY memory_wave IS
END memory_wave;

ARCHITECTURE testbench_arch OF memory_wave IS
-- If you get a compiler error on the following line,
-- from the menu do Options->Configuration select VHDL 87
FILE RESULTS: TEXT OPEN WRITE_MODE IS "results.txt";
	COMPONENT memory
		PORT (
			T3 : In  std_logic;
			MRD_C : In  std_logic;
			MWR_C : In  std_logic;
			Rtemp : Out  std_logic_vector (7 DOWNTO 0);
			data : In  std_logic_vector (7 DOWNTO 0);
			nMRD : Out  std_logic;
			nMWR : Out  std_logic
		);
	END COMPONENT;

	SIGNAL T3 : std_logic;
	SIGNAL MRD_C : std_logic;
	SIGNAL MWR_C : std_logic;
	SIGNAL Rtemp : std_logic_vector (7 DOWNTO 0);
	SIGNAL data : std_logic_vector (7 DOWNTO 0);
	SIGNAL nMRD : std_logic;
	SIGNAL nMWR : std_logic;

BEGIN
	UUT : memory
	PORT MAP (
		T3 => T3,
		MRD_C => MRD_C,
		MWR_C => MWR_C,
		Rtemp => Rtemp,
		data => data,
		nMRD => nMRD,
		nMWR => nMWR
	);

	PROCESS
		VARIABLE TX_OUT : LINE;
		VARIABLE TX_ERROR : INTEGER := 0;

		PROCEDURE CHECK_Rtemp(
			next_Rtemp : std_logic_vector (7 DOWNTO 0);
			TX_TIME : INTEGER
		) IS
			VARIABLE TX_STR : String(1 to 4096);
			VARIABLE TX_LOC : LINE;
		BEGIN
			-- If compiler error ("/=" is ambiguous) occurs in the next line of code
			-- change compiler settings to use explicit declarations only
			IF (Rtemp /= next_Rtemp) THEN 
				STD.TEXTIO.write(TX_LOC,string'("Error at time="));
				STD.TEXTIO.write(TX_LOC, TX_TIME);
				STD.TEXTIO.write(TX_LOC,string'("ns Rtemp="));
				IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, Rtemp);
				STD.TEXTIO.write(TX_LOC, string'(", Expected = "));
				IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, next_Rtemp);
				STD.TEXTIO.write(TX_LOC, string'(" "));
				TX_STR(TX_LOC.all'range) := TX_LOC.all;
				STD.TEXTIO.writeline(results, TX_LOC);
				STD.TEXTIO.Deallocate(TX_LOC);
				ASSERT (FALSE) REPORT TX_STR SEVERITY ERROR;
				TX_ERROR := TX_ERROR + 1;
			END IF;
		END;

		PROCEDURE CHECK_nMRD(
			next_nMRD : std_logic;
			TX_TIME : INTEGER
		) IS
			VARIABLE TX_STR : String(1 to 4096);
			VARIABLE TX_LOC : LINE;
		BEGIN
			-- If compiler error ("/=" is ambiguous) occurs in the next line of code
			-- change compiler settings to use explicit declarations only
			IF (nMRD /= next_nMRD) THEN 
				STD.TEXTIO.write(TX_LOC,string'("Error at time="));
				STD.TEXTIO.write(TX_LOC, TX_TIME);
				STD.TEXTIO.write(TX_LOC,string'("ns nMRD="));
				IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, nMRD);
				STD.TEXTIO.write(TX_LOC, string'(", Expected = "));
				IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, next_nMRD);
				STD.TEXTIO.write(TX_LOC, string'(" "));
				TX_STR(TX_LOC.all'range) := TX_LOC.all;
				STD.TEXTIO.writeline(results, TX_LOC);
				STD.TEXTIO.Deallocate(TX_LOC);
				ASSERT (FALSE) REPORT TX_STR SEVERITY ERROR;
				TX_ERROR := TX_ERROR + 1;
			END IF;
		END;

		PROCEDURE CHECK_nMWR(
			next_nMWR : std_logic;
			TX_TIME : INTEGER
		) IS
			VARIABLE TX_STR : String(1 to 4096);
			VARIABLE TX_LOC : LINE;
		BEGIN
			-- If compiler error ("/=" is ambiguous) occurs in the next line of code
			-- change compiler settings to use explicit declarations only
			IF (nMWR /= next_nMWR) THEN 
				STD.TEXTIO.write(TX_LOC,string'("Error at time="));
				STD.TEXTIO.write(TX_LOC, TX_TIME);
				STD.TEXTIO.write(TX_LOC,string'("ns nMWR="));
				IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, nMWR);
				STD.TEXTIO.write(TX_LOC, string'(", Expected = "));
				IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, next_nMWR);
				STD.TEXTIO.write(TX_LOC, string'(" "));
				TX_STR(TX_LOC.all'range) := TX_LOC.all;
				STD.TEXTIO.writeline(results, TX_LOC);
				STD.TEXTIO.Deallocate(TX_LOC);
				ASSERT (FALSE) REPORT TX_STR SEVERITY ERROR;
				TX_ERROR := TX_ERROR + 1;
			END IF;
		END;

		BEGIN
		-- --------------------
		T3 <= transport '0';
		MRD_C <= transport '0';
		MWR_C <= transport '0';
		data <= transport std_logic_vector'("00000000"); --0
		-- --------------------
		WAIT FOR 100 ns; -- Time=100 ns
		T3 <= transport '1';
		MRD_C <= transport '1';
		data <= transport std_logic_vector'("10101011"); --AB
		-- --------------------
		WAIT FOR 100 ns; -- Time=200 ns
		T3 <= transport '0';
		MRD_C <= transport '0';
		data <= transport std_logic_vector'("00000000"); --0
		-- --------------------
		WAIT FOR 100 ns; -- Time=300 ns
		T3 <= transport '1';
		MWR_C <= transport '1';
		-- --------------------
		WAIT FOR 100 ns; -- Time=400 ns
		T3 <= transport '0';
		MWR_C <= transport '0';
		-- --------------------
		WAIT FOR 300 ns; -- Time=700 ns
		-- --------------------

		IF (TX_ERROR = 0) THEN 
			STD.TEXTIO.write(TX_OUT,string'("No errors or warnings"));
			STD.TEXTIO.writeline(results, TX_OUT);
			ASSERT (FALSE) REPORT
				"Simulation successful (not a failure).  No problems detected. "
				SEVERITY FAILURE;
		ELSE
			STD.TEXTIO.write(TX_OUT, TX_ERROR);
			STD.TEXTIO.write(TX_OUT, string'(
				" errors found in simulation"));
			STD.TEXTIO.writeline(results, TX_OUT);
			ASSERT (FALSE) REPORT
				"Errors found during simulation"
				SEVERITY FAILURE;
		END IF;
	END PROCESS;
END testbench_arch;

CONFIGURATION memory_cfg OF memory_wave IS
	FOR testbench_arch
	END FOR;
END memory_cfg;