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Logic Analyzer 的代码
ext2_25to32.vhd
Library IEEE;
use IEEE.std_logic_1164.all;
entity EXT2_25to32 is
port (
MANSUM25: in std_logic_vector (24 downto 0);
LEFTDIN : out std_logic_vector (31 downto 0)
ext_25to32.vhd
Library IEEE;
use IEEE.std_logic_1164.all;
entity EXT_25to32 is
port (
TOSHIFT: in std_logic_vector (24 downto 0);
RIGHTDIN : out std_logic_vector (31 downto 0)
)
leadsign.vhd
Library IEEE;
use IEEE.std_logic_1164.all;
entity LEADSIGN is
port (
DIN : in std_logic_vector(24 downto 0);
CNT : out std_logic_vector(4 downto 0)
);
end LEADSIG
adjust.vhd
Library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity ADJUST is
port (
MANSUM: in std_logic_vector (25 downto 0);
MANSFT: in std_logic_vector (
vote7.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity vote7 is
port(a:in std_logic_vector(6 downto 0);
p,np:out std_logic);
end v
renbjq.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity renbjq is
port(d:in std_logic_vector(6 downto 0);
green,red:out std_logic);
sdr_sdram.vhd
--#######################################################################
--
-- LOGIC CORE: SDR SDRAM Controller
-- MODULE NAME: sdr_sdram()
-- COMPANY: Alte
notetabs.vhd
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 17:39:05 01/10/2009
-- Design Name:
-- Module Name: NoteTabs -
top .vhd
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 17:40:23 01/10/2009
-- Design Name:
-- Module Name: TOP - Beh
addr.vhd
--addr (模块)正弦
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity addr is
port(
clk:in std_logic;
dout:out std_logic_vector(5 downto 0)
);
end ad