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Logic Analyzer 的代码
chushu.vhd
library ieee;
use ieee.std_logic_1164.all;
entity chushu is
port (x:in std_logic;
m1 :out std_logic_vector (23 downto 0)
);
end chushu;
ARCHITECTURE ART OF chushu IS
begin
m1
core_fft64.vho
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used --
-- solely for design, simulation
symulacja.vhd
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 15:00:52 01/26/2009
-- Design Name: led
-- Module Name: C:/D
说明.txt
此为实验1 简单逻辑电路设计与仿真例程：
logic_7474为D触发器设计的4进制加法计数器。
logic_encoder为2-4译码器。
在软件中将图制好后进行编译与仿真，打开软件中的波形仿真介面自己设置一些输入后进行编译分析一下输出波形是否正确
antishakeswitchprocedure.txt
开关防抖程序
library ieee;
use ieee.std_logic_1164.all;
entity dou is
port(din,clk: in std_logic;
dout: out std_logic);
end dou;
architecture beha of dou is
signal x,y:std_logic;
i60bcd.vhd
--The IEEE standard 1164 package, declares std_logic, rising_edge(), etc.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity i60bcd i
regne.vhd
--regne.vhd n-bit register with enable
library ieee ;
use ieee.std_logic_1164.all ;
entity regne is
generic ( n : integer := 12 ) ;
port (
r : in std_logic_vector(n-1 downto 0) ;--register
negative.vhd
--negative.vhd correct negative number circuit
library ieee ;
use ieee.std_logic_1164.all;
use work.components.all;
entity negative is
port(
a : in std_logic_vector(11 downto 0);--块
bcdadd.vhd
--bcdadd.vhd 1 digit bcd adder
library ieee ;
use ieee.std_logic_1164.all;
use work.components.all;
entity bcdadd is
port(
a : in std_logic_vector(3 downto 0);--砆
bcd.vhd
--bcd.vhd 1 digits bcd adder/subtractor
library ieee ;
use ieee.std_logic_1164.all;
use work.components.all;
entity bcd is
port(
a : in std_logic_vector(3 downto 0);--砆