chushu.vhd

来自「用FPGA做的DDS函数信号发生器」· VHDL 代码 · 共 12 行

library ieee;
use ieee.std_logic_1164.all;
entity chushu is 
port (x:in std_logic;
      m1 :out std_logic_vector (23 downto 0)
      );
end chushu;
ARCHITECTURE ART OF chushu IS
begin
   m1<="111111111111111111111111";
   
end art;