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找到约 10,000 项符合
Logic Analyzer 的代码
v10_9.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
-- synopsys translate_off
Library XilinxCoreLib;
-- synopsys translate_on
entity RAMTest is
port(addr : IN std_l
v10_12.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity Fix2Flt is
port(AddO : in std_logic_vector(24 downto 0);
DOut : out std_logic_vector(31 do
v15_2.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_signed.all;
use std.textio.all;
entity tb_M16x16 is
end tb_M16x16;
architecture a_tb_M16x16 of tb
v15_1.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_signed.all;
use std.textio.all;
entity tb_M16x16 is
end tb_M16x16;
architecture a_tb_M16x16 of tb
serout.vhd
LIBRARY ieee ;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
ENTITY dctslowout IS
PORT(
clk : IN std_logic ;
doutput : IN std_logic_vector (15 DOWNTO
leddongtai.vhd
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
ENTITY leddongtai IS
PORT
(
clock :IN STD_LOGIC; --clock is 1KHZ
flash : IN STD_LOGIC;
ewh,ewl,snh,snl : IN
clk_div.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
ENTITY clk_div IS
PORT(CLK:IN STD_LOGIC;
clk_div3:OUT STD_LOGIC);
END clk
shifter.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity shifter is
port(clk:in std_logic;
input :in std_logic_vector(2 downto 0);
output :out std_l
shifter.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity shifter is
port(clk:in std_logic;
input :in std_logic_vector(2 downto 0);
output :out std_l
clk_div.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity clk_div is
port(clk : in std_logic;
clk_div6 : out std_logic);
end clk_div