v15_1.vhd

台湾全华科技VHDL教材实例

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_signed.all;
use std.textio.all;

entity tb_M16x16 is
end tb_M16x16;

architecture a_tb_M16x16 of tb_M16x16 is

	component M16x16
	port(InA		: in  std_logic_vector(15 downto 0);
	     InB		: in  std_logic_vector(15 downto 0);
	     DOut   	: out std_logic_vector(31 downto 0);
	     Clk    	: in  std_logic);
	end component;  
	
	signal InA	  :  std_logic_vector(15 downto 0);   
	signal InB	  :  std_logic_vector(15 downto 0);   
	signal DOut   :  std_logic_vector(31 downto 0); 
	signal SOut   :  integer;
	signal SOutD  :  integer;
	signal Clki   :  std_logic := '1';    
	signal Clk    :  std_logic := '1';  
	signal reset  :  std_logic := '0';                    

begin

	dut : M16x16
	port map(InA		=> InA	 ,
	        InB		=> InB	 ,
	        DOut   	=> DOut  ,
	        Clk    	=> Clk   );
	         
	clki <= not clki after 10 ns;
	Clk <= Clki when reset = '1' else
	       '1';	  
	reset <= '1' after 100 ns;
	       
	process
		file Data14_1 : text open read_mode is "D14_1.dat"; 
		variable DLine : line;
		variable DataA : integer;
		variable DataB : integer;
		variable DataOut : integer;
	begin
		wait until Clk = '1' and Clk'event;
			readline(Data14_1,DLine);
			read(DLine,DataA);
			read(DLine,DataB);
			read(DLine,DataOut);
			InA <= CONV_STD_LOGIC_VECTOR(DataA,16);
			InB <= CONV_STD_LOGIC_VECTOR(DataB,16);
			SOut <= DataOut;
			SOutD <= SOut;
			if SOutD /= DOut then
			    assert false report "Two values are not the same"
    			severity error; 
			end if;
	end process;

end a_tb_M16x16;