shifter.vhd

基于VHDL设计的在quarters2上的循环码编码器

library ieee;   
use ieee.std_logic_1164.all;  
use ieee.std_logic_unsigned.all;   
entity shifter is   
port(clk:in  std_logic;   
input  :in  std_logic_vector(2 downto 0);   
output :out std_logic_vector(6 downto 0));  
end shifter;   
architecture behave_shifter of shifter is 
signal d: std_logic_vector(3 downto 0); 
signal temp: std_logic;
begin 
process(clk)   
begin  
output0<=input0;
temp<=d3 xor output0;
d3<=d2,d2<=d1 xor temp;
d1<=d0 xor temp;
d0<=temp;
output1<=input1;
temp<=d3 xor output1;
d3<=d2,d2<=d1 xor temp;
d1<=d0 xor temp;
d0<=temp;
output2<=input2;
temp<=d3 xor output2;
d3<=d2,d2<=d1 xor temp;
d1<=d0 xor temp;
d0<=temp;

output(3)<=d(3),
d(3)<=d(2);d(2)<=d(1);
d(1)<=d(0);
d(0)<='0';
output(4)<=d(3),
d(3)<=d(2);d(2)<=d(1);
d(1)<=d(0);
d(0)<='0';
output(5)<=d(3),
d(3)<=d(2);d(2)<=d(1);
d(1)<=d(0);
d(0)<='0';
output(6)<=d(3),
d(3)<=d(2);d(2)<=d(1);
d(1)<=d(0);
d(0)<='0';
output(7)<=d(3),
d(3)<=d(2);d(2)<=d(1);
d(1)<=d(0);
d(0)<='0';
end begin;
end begin;
  
    end process; 
 end behave_shifter;