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Logic Analyzer 的代码
vhdl code8.vhd
library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;
entity counter is port(C, CLR : in std_logic; Q : out std_logic_vector(3 downto 0)); end counter;architecture archi
vhdl code5.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY ffT IS
PORT(T,CLK1,RESET:IN BIT;
Q,QINV:OUT BIT);
END ffT;
ARCHITECTURE behav OF ffT IS
SIGNAL S:BIT;
BEGIN
PROCESS
BEGIN
WAIT UNTIL CLK='1
lx8.vhd
library ieee;
use ieee.std_logic_1164.all;
entity lx8 is
port(a :in std_logic_vector(2 downto 0);
g1,g2a,g2b :in std_logic;
l :out std_logic_vector(7 dow
vb48.vhd
library ieee;
use ieee.std_logic_1164.all;
entity vb48 is
port(a :in std_logic_vector(3 downto 0);
bin :in std_logic;
y :out std_logic_vector(
lx38.vhd
library ieee;
use ieee.std_logic_1164.all;
entity lx38 is
port(a,b,c :in std_logic;
g1,g2a,g2b :in std_logic;
l :out std_logic_vector(7 downto 0));
end
ad0804.c
///////////////////////////
///A/D转换实验
///////////////////
#include
#include
//********************************************
//LIBRARY IEEE;
//USE IEEE.STD_LOGIC_1164.ALL;
yimaqi.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
----------------------------------------
entity yimaqi is
port(F2,F1:in std_logic;
Y3,Y2,Y1,Y0:out std_logic);
e
count16.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
--------------------------------------------------
entity count16 is
port(clk:in std_logic;
D,C,B,A:out std_logi
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity maindec is
generic(
idle : integer := 0;
ifetch : integer := 1;
decode : integer := 2;
cfgtaddr_cardbus.vhd
--------------------------------------------------------------------------------
--
-- File : cfgtaddr_cardbus.vhd
-- Last Modification: 01/27/2004
--
-- Created In SpDE Version: SpDE 9.5.1
-- A