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找到约 10,000 项符合
Logic Analyzer 的代码
mcutofpga.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity McuToFpga is
generic(QWidth : Integer := 24); --移位寄存器的宽度
port(
CLK: in std_logic; --同步时钟,上升研写入数据
DA
dds.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity dds is
port(
frep: in std_logic_vector(14 downto 0);
phase: in std_logic_vector(8 downto 0);
myfunction.vhd
Library IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
package MyFunc IS
Function max(L, R: INTEGER) return INTEGER ;
Function "+"(L:STD_LOGIC_VECTOR;R:STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
END Pac
shuzi.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY SHUZI IS
PORT(DIAO,GONG,RST,CLK1,CLK2:IN STD_LOGIC;
C0:OUT STD_LOGIC;
Y:OUT STD_LOGIC_VECTOR
sm.vhd.bak
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY SM IS
PORT(CLK2:IN STD_LOGIC;
MIAO,FEN,SHI:IN STD_LOGIC_VECTOR (7 DOWNTO 0);
Y: OUT STD_LOGIC_VECTOR
sm.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY SM IS
PORT(CLK2:IN STD_LOGIC;
MIAO,FEN,SHI:IN STD_LOGIC_VECTOR (7 DOWNTO 0);
Y: OUT STD_LOGIC_VECTOR
sm.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY SM IS
PORT(CLK2:IN STD_LOGIC;
MIAO,FEN,DIAN:IN STD_LOGIC_VECTOR (7 DOWNTO 0);
Y: OUT STD_LOGIC_VECTOR
time.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity time is
port(clk:in std_logic; --时钟500Hz
reset:in std_logic; --复位信号
start:in std_logic;
sram.vhd
---------------------------------------------------------------------------------------------------
--*************************************************************************************************
frequency.vhd
---------------------------------------------------------------------------------------------------
--*************************************************************************************************