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Logic Analyzer 的代码
计数器：generate语句的应用.txt
-- Generated Binary Up Counter
-- The first design entity is a T-type flip-flop.
-- The second is an scalable synchronous binary up counter illustrating the use of the generate statement to produce
带load、clr等功能的寄存器2.txt
--
--
---------------------------------------------------------------------------------------
-- DESCRIPTION : Shift register
-- Type : univ
-- Width : 4
--
miniuart.vhd
--===========================================================================--
--
-- S Y N T H E Z I A B L E miniUART C O R E
--
-- www.OpenCores.Org - January 2000
-- This core adheres
miniuart.vhd
--===========================================================================--
--
-- S Y N T H E Z I A B L E miniUART C O R E
--
-- www.OpenCores.Org - January 2000
-- This core adheres
control_fsm_.vhd
-------------------------------------------------------------------------------
-- --
-- X X XXXXXX XXXXXX
mux8.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity mux8 is
port(
a,b,c,d,e,f:in std_logic_vector(3 downto 0);
clk:in std_logi
cnn.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity cnn is
port(clk :in std_logic;
dataout:out std_logic_vector(31 downto 0));
end cnn;
architecture aa
and2.vhd
library ieee;
use ieee.std_logic_1164.all;
entity andd is
port(x,y:in std_logic;
z:out std_logic_vector(1 downto 0));
end andd;
architecture andd of andd is
begin
z
psk.vhd
library ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
entity PSK is
port(clk,enable:in std_logic;
x: in std_logic_vector(11 downto 0);
q:out std_logic_vector(1
ask.vhd
library ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
entity ASK is
port(clk,enable:in std_logic;
x: in std_logic_vector(11 downto 0);
q:out std_logic_vector(1