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Logic Analyzer 的代码
bcd3.vhd
--bcd3.vhd 3 digits bcd adder/subtractor
library ieee ;
use ieee.std_logic_1164.all;
use work.components.all;
entity bcd3 is
port(
a : in std_logic_vector(11 downto 0);--砆
memtest.vhd
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use WORK.common.all;
use WORK.rand.all;
package mem is
component memTest
generic(
DATA_WIDTH : natura
dual_reg4.vhd
library ieee;
use ieee.std_logic_1164.all;
entity dual_reg4 is
port(a:in std_logic_vector(3 downto 0);
b:in std_logic_vector(3 downto 0);
clk:in std_logic;
lda:in std_
dual_reg4.vhd
library ieee;
use ieee.std_logic_1164.all;
entity dual_reg4 is
port(a:in std_logic_vector(3 downto 0);
b:in std_logic_vector(3 downto 0);
clk:in std_logic;
lda:in std_
dual_reg4.vhd
library ieee;
use ieee.std_logic_1164.all;
entity dual_reg4 is
port(a:in std_logic_vector(3 downto 0);
b:in std_logic_vector(3 downto 0);
clk:in std_logic;
lda:in std_
cnt6.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY CNT6 IS
PORT(CLK: IN STD_LOGIC;
CLR: IN STD_LOGIC;
ENA: IN STD_LOGIC;
CQ: OUT STD_LOGIC_VECTOR(3 DOWNT
pulse.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY PULSE IS
PORT(CLK: IN STD_LOGIC;
A,B: IN STD_LOGIC_VECTOR(7 DOWNTO 0);
PSOUT: OUT STD_LOGIC);
END ENTI
time.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY TIMES IS
PORT(CLR: IN STD_LOGIC;
CLK: IN STD_LOGIC;
ENA: IN STD_LOGIC;
DOUT: OUT STD_LOGIC_VECTOR(23 DOWNTO 0));
END ENT
shift register.vhd
library ieee;
use ieee.std_logic_1164.all;
Entity ShiftReg is
port(
s,clk1:in std_logic;
reset1:in std_logic;
Q2:out std_logic_vector(3 downto 0)
counter.vhd
library ieee;
use ieee.std_logic_1164.all;
Entity Counter is
port(
clk1:in std_logic;
reset1:in std_logic;
Q2:out std_logic_vector(3 downto 0)