pulse.vhd

来自「EDA技术应用.用QUARTUES II 实现EDA技术实验操作,类似于精典的M」· VHDL 代码 · 共 40 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY PULSE IS
      PORT(CLK: IN STD_LOGIC;
                  A,B: IN STD_LOGIC_VECTOR(7 DOWNTO 0);
                  PSOUT: OUT STD_LOGIC);
END ENTITY PULSE;
ARCHITECTURE ART OF PULSE IS
  COMPONENT LCNT8 IS
              PORT(CLK, LD: IN STD_LOGIC;
                         D: IN STD_LOGIC_VECTOR(7 DOWNTO 0);
                         CAO: OUT STD_LOGIC);
END COMPONENT LCNT8;
SIGNAL CAO1, CAO2 : STD_LOGIC;
SIGNAL LD1, LD2 :STD_LOGIC;
SIGNAL PSINT: STD_LOGIC;
BEGIN
U1: LCNT8 PORT MAP(CLK=>CLK, LD=>LD1, D=>A, CAO=>CAO1);
U2: LCNT8 PORT MAP(CLK=>CLK, LD=>LD2, D=>B, CAO=>CAO2);
PROCESS(CAO1,CAO2)IS
BEGIN
IF CAO1='1' THEN PSINT<='0';
ELSIF CAO2'EVENT AND CAO2='1' THEN PSINT<='1';
END IF;
END PROCESS;
LD1<=NOT PSINT; LD2<=PSINT; PSOUT<=PSINT;
END  ARCHITECTURE ART;