cnt6.vhd

来自「EDA技术应用.用QUARTUES II 实现EDA技术实验操作,类似于精典的M」· VHDL 代码 · 共 31 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY CNT6 IS
  PORT(CLK: IN STD_LOGIC;
  CLR: IN STD_LOGIC;
  ENA: IN STD_LOGIC;
  CQ: OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
  CARRY_OUT: OUT STD_LOGIC);
END ENTITY CNT6;
ARCHITECTURE ART OF CNT6 IS
  SIGNAL CQI: STD_LOGIC_VECTOR(3 DOWNTO 0);
  BEGIN
  PROCESS(CLK,CLR,ENA) IS
  BEGIN
    IF CLR='1' THEN CQI<="0000";
    ELSIF CLK'EVENT AND CLK='1' THEN
       IF ENA='1' THEN
          IF CQI="0101" THEN CQI<="0000";
             ELSE CQI<=CQI+'1';END IF;
       END IF;
    END IF;
    END PROCESS;
    PROCESS(CQI) IS
    BEGIN
       IF CQI="0000" THEN CARRY_OUT<='1';
          ELSE CARRY_OUT<='0'; END IF;
    END PROCESS;
    CQ<=CQI;
END ARCHITECTURE ART;