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找到约 10,000 项符合
Logic Analyzer 的代码
tonetaba.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY ToneTaba IS
PORT ( Index : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
CODE : OUT STD_LOGIC_VECTOR (3 DOWNTO 0) ;
HIGH : OUT STD_LOGIC;
Tone : O
songer.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY Songer IS
PORT ( CLK12MHZ : IN STD_LOGIC;
CLK8HZ : IN STD_LOGIC;
CODE1 : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
HIGH1 : OUT STD_LOGIC;
notetabs.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY NoteTabs IS
PORT ( clk : IN STD_LOGIC;
ToneIndex : OUT STD_LOGIC_VECTOR (3 DOWNTO 0) );
END;
ARCHITECTURE
xxx.vhd
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 15:21:47 11/08/2006
-- Design Name: xccpld
-- Module Name: x
writefifo.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for ins
i60bcd.vhd
--The IEEE standard 1164 package, declares std_logic, rising_edge(), etc.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity i60bcd i
regne.vhd
--regne.vhd n-bit register with enable
library ieee ;
use ieee.std_logic_1164.all ;
entity regne is
generic ( n : integer := 12 ) ;
port (
r : in std_logic_vector(n-1 downto 0) ;--register
negative.vhd
--negative.vhd correct negative number circuit
library ieee ;
use ieee.std_logic_1164.all;
use work.components.all;
entity negative is
port(
a : in std_logic_vector(11 downto 0);--块
bcdadd.vhd
--bcdadd.vhd 1 digit bcd adder
library ieee ;
use ieee.std_logic_1164.all;
use work.components.all;
entity bcdadd is
port(
a : in std_logic_vector(3 downto 0);--砆
bcd.vhd
--bcd.vhd 1 digits bcd adder/subtractor
library ieee ;
use ieee.std_logic_1164.all;
use work.components.all;
entity bcd is
port(
a : in std_logic_vector(3 downto 0);--砆