代码搜索结果
找到约 10,000 项符合
Logic Analyzer 的代码
cic_v7_2.vhd
-- megafunction wizard: %CIC v7.2%
-- GENERATION: XML
-- ============================================================
-- Megafunction Name(s):
-- cic_v7_2_cic
-- ============================
cic_v7_2.vhd
-- megafunction wizard: %CIC v7.2%
-- GENERATION: XML
-- ============================================================
-- Megafunction Name(s):
-- cic_v7_2_cic
-- ============================
ﾣë.vhd
-- TestBench Template
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY testbench IS
END testbench;
ARCHITECTURE behavior OF testbench IS
-- Co
pn.vhd
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 14:36:59 03/29/07
-- Design Name:
-- Module Name: pn - B
pipemult.vhd
-- Copyright (C) 1991-2005 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and
count.vhd
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity count is
port(clk_1:in std_logic; --1HZ输入
sw:in std_logic; --状态判断输入
player1,player2:in
count.vhd.bak
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity count is
port(clk,clr,en:in std_logic;
q: out std_logic_vector (3
count.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity count is
port(clk,clr,en:in std_logic;
q: out std_logic_vector (3
vhdl1.vhd.bak
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity count is
port(clk,clr,en:in std_logic;
q: out std_logic_vector (3
cic_v6_1.vhd
-- megafunction wizard: %CIC v6.1%
-- GENERATION: XML
-- ============================================================
-- Megafunction Name(s):
-- cic_v6_1_cic
-- ============================