代码搜索结果
找到约 10,000 项符合
Logic Analyzer 的代码
yimaqi.vhd
library ieee ;
use ieee.std_logic_1164.all ;
use ieee.std_logic_unsigned.all ;
entity yimaqi is
port(F1,F2:in std_logic;
Y3,Y2,Y1,Y0:out std_logic
);
end yimaqi ;
architecture behv of y
serial.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
-- Uncomment the following lines to use the declarations that are
-- provided for instantia
interface.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for instantia
mux.vhd
-------------------------------------------------------------------------------
-- Title : mux
-- Project :
-------------------------------------------------------------------------------
--
conj.vhd
-------------------------------------------------------------------------------
-- Title : Conj.vhd
-- Project :
------------------------------------------------------------------------------
parallel.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
-- Uncomment the following lines to use the declarations that are
-- provided for instantia
freqtest8.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY FREQTEST8 IS
PORT (CLK1HZ : IN std_logic;
FSIN : IN std_logic;
DOUT : OUT std_logic_VECTOR(31 DOWNTO 0));
END FREQTEST8;
ARCHIT
reg32b.vhd
LIBRARY IEEE; --32位锁存器
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY REG32B IS
PORT ( LK : IN STD_LOGIC;
DIN : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
dvf.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY DVF IS
PORT ( CLK : IN STD_LOGIC;
D : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
FOUT : OUT STD_LOG
declcnt.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY DECLCNT IS
PORT (CLK0,RST0,EN0 : IN STD_LOGIC;
LED7S : OUT STD_LOGIC_VECTOR(6 DOWNTO 0);