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Logic Analyzer 的代码
mux4w16.vhd
-- output of CoreGen module generator
-- $Header: mux4VHT.vhd,v 1.2 1998/06/15 17:58:03 tonyw Exp $
-- ************************************************************************
-- Copyright 1996-19
adder4.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for ins
wishbone_i2c_master.vhd
--
-- WISHBONE revB2 compiant I2C master core
--
-- author: Richard Herveille
-- rev. 0.1 based on simple_i2c
-- rev. 0.2 april 27th 2001, fixed incomplete sensitivity list on assign_dato process (tha
53_counter.vhd
library IEEE;
use IEEE.std_logic_1164.all;
package mycntpkg is
component count port(clk,rst : in std_logic;
cnt : inout std_logic_vector(2 downto 0));
end component;
end mycntpkg;
cnt10b.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity cnt10b is
port(lock0,clr,clk,we:in std_logic;
dout:out std_logic_vector(8 downto 0);
clkout:out std_
cnt10b.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity cnt10b is
port(lock0,clr,clk,we:in std_logic;
dout:out std_logic_vector(8 downto 0);
clkout:out std_
l_conversions_p.vhd
-- Altera Microperipheral Reference Design Version 0802
--------------------------------------------------------------------------------
-- File Name: l_conversions_p.vhd
-------------------------
decode.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for ins
d2_4l
--------------------------------------------------------------------------------
-- Copyright (c) 1995-2003 Xilinx, Inc.
-- All Right Reserved.
-----------------------------------------------------
dq024.vhd
--------------------------------------------------------------------------------
-- Copyright (c) 1995-2003 Xilinx, Inc.
-- All Right Reserved.
-----------------------------------------------------