d2_4l

xilinx xc9572 cpld 实现的伺服电机控制器

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-- Copyright (c) 1995-2003 Xilinx, Inc.
-- All Right Reserved.
--------------------------------------------------------------------------------
--   ____  ____ 
--  /   /\/   / 
-- /___/  \  /    Vendor: Xilinx 
-- \   \   \/     Version : 6.3i
--  \   \         Application : 
--  /   /         Filename : xil_1076_5
-- /___/   /\     Timestamp : 04/03/2006 09:13:06
-- \   \  /  \ 
--  \___\/\___\ 
--
--Command: 
--Design Name: d3_8l
--

library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
-- synopsys translate_off
library UNISIM;
use UNISIM.Vcomponents.ALL;
-- synopsys translate_on

entity d2_4l is
   port ( A0 : in    std_logic; 
          A1 : in    std_logic; 
          A2 : in    std_logic; 
          E  : in    std_logic; 
          D0 : out   std_logic; 
          D1 : out   std_logic; 
          D2 : out   std_logic; 
          D3 : out   std_logic);
end d2_4l;

architecture BEHAVIORAL of d2_4l is
signal  addr: std_logic_vector (2 downto 0);
signal  Dout: std_logic_vector (3 downto 0);
begin
  addr<=A2 & A1 & A0;
  process(addr,E) 
  begin
  if(E='1') then
    Dout<="11111111";
  else
    case addr  is
	  
	    when  "000"=> Dout<="1110"; 
	    when  "001"=> Dout<="1101";
	    when  "010"=> Dout<="1011";
	    when  "100"=> Dout<="0111";
	    when  "101"=> Dout<="0111";
	    when  "110"=> Dout<="0111";
	    when  "111"=> Dout<="0111";
       when others=> Dout<="1111";
	 end case; 
  end if;
  end  process;
 
 D0<=Dout(0);
 D1<=Dout(1);
 D2<=Dout(2);
 D3<=Dout(3);
end BEHAVIORAL;