adder4.vhd

来自「实验课的作业」· VHDL 代码 · 共 40 行

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity adder4 is
Port ( 
X : in std_logic_vector(3 downto 0);
Y : in std_logic_vector(3 downto 0);
S : out std_logic_vector(3 downto 0);
Cin : in std_logic;	   
Cout : out std_logic);
end adder4;

architecture Behavioral of adder4 is

component fulladder port  (
	A, B, Cin: in std_logic; -- Three binary inputs
	S, Cout: out std_logic); -- Two binary outputs  
end component;

SIGNAL a : std_logic_vector(2 downto 0);	 


begin 
	U1: fulladder port map (X(0),Y(0),Cin,S(0),a(0));

	U2: fulladder port map (X(1),Y(1),a(0),S(1),a(1));

	U3: fulladder port map (X(2),Y(2),a(1),S(2),a(2));

	U4: fulladder port map (X(3),Y(3),a(2),S(3),Cout);
		
end Behavioral;