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Logic Analyzer 的代码
idec.vhd
--
-- Risc5x
-- www.OpenCores.Org - November 2001
--
--
-- This library is free software; you can distribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as pu
traffic.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity traffic is
port(clk : in std_logic;
ql : out std_logic_vector(7 downto 0);
divider.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity last is
Port ( sel : in std_logic_vector(3 downto 0);
clk : in
malvino.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity conter is
Port ( clk : in std_logic;
en: in std_logic;
cnt
shift.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity shift is
port(
clk:in std_logic;
do:out std_logic_vector(1 downto 0)
run.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity runled is
port(clk:in std_logic;
put:out std_logic_vector(6 downto 0));
e
扫描 (2).txt
library altera;
use altera.maxplus2.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity keyctrl is
port( clk,reset:in std_l
i2c_master.vhd
--
-- WISHBONE revB2 compiant I2C master core
--
-- author: Richard Herveille
-- rev. 0.1 based on simple_i2c
-- rev. 0.2 april 27th 2001, fixed incomplete sensitivity list on assign_dato process (tha
addsubc.vhd
-------------------------------------------------------------------------------
-- Title : Parallel-prefix adder-subtractor with carry-in, carry-out
-- Project : VHDL Library of Arithmetic U
addsubv.vhd
-------------------------------------------------------------------------------
-- Title : Parallel-prefix adder-subtractor with carry-in, overflow flag
-- Project : VHDL Library of Arithmet