📄 扫描 (2).txt
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library altera;
use altera.maxplus2.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity keyctrl is
port( clk,reset:in std_logic;
vv:in std_logic_vector(3 downto 0); --vv1-vv4
vh:inout std_logic_vector(3 downto 0); --vh1-vh4
show:out std_logic_vector(6 downto 0); --led(0)-led(6)
row:out std_logic;
d_in:in std_logic;
d_out:out std_logic); --选择一个数码管
end keyctrl;
architecture behav of keyctrl is
signal showout:std_logic_vector(6 downto 0);
signal keydown:std_logic_vector(7 downto 0);
signal q:std_logic_vector(21 downto 0);
signal clk1:std_logic;
begin
row<='1';
p0: process(clk)
begin
if clk'event and clk='1' then
q<=q+1;
end if;
end process p0;
clk1 <= q(7);
p1: process(clk)
variable counter:integer range 0 to 3; --键盘扫描计数
begin
if reset='1'then counter:=0;
elsif clk'event and clk='1'then
if counter=3 then counter:=0;
else counter:=counter+1;
end if;
case counter is
when 0=> vh<="1110"; --选中vh1
when 1=> vh<="1101"; --选中vh2
when 2=> vh<="1011"; --选中vh3
when 3=> vh<="0111"; --选中vh4
end case;
keydown<=vh&vv;
case keydown is
when "11101110"=>showout<="0111111"; --0 vh1&vv1
when "11101101"=>showout<="0000110"; --1 vh1&vv2
when "11101011"=>showout<="1011011"; --2 vh1&vv3
when "11100111"=>showout<="1001111"; --3 vh1&vv4
when "11011110"=>showout<="1100110"; --4 vh2&vv1
when "11011101"=>showout<="1101101"; --5 vh2&vv2
when "11011011"=>showout<="1111101"; --6 vh2&vv3
when "11010111"=>showout<="0000111"; --7 vh2&vv4
when "10111110"=>showout<="1111111"; --8 vh3&vv1
when "10111101"=>showout<="1101111"; --9 vh3&vv2
when "10111011"=>showout<="1110111"; --A vh3&vv3
when "10110111"=>showout<="1111100"; --B vh3&vv4
when "01111110"=>showout<="0111001"; --C vh4&vv1
when "01111101"=>showout<="1011110"; --D vh4&vv2
when "01111011"=>showout<="1111001"; --E vh4&vv3
when "01110111"=>showout<="1110001"; --F vh4&vv4
when others=>null;
end case;
end if;
end process;
show<=showout;
end behav;
architecture a of keyctrl IS
signal vcc, inv_d : std_logic ;
signal q0, q1 : std_logic ;
signal d1, d0 : std_logic ;
begin
vcc <= '1' ;
inv_d <= not d_in ;
dff1 : dff port map (d =>vcc , q => q0 , clk => clk, clrn =>inv_d , prn => vcc);
dff2 : dff port map (d =>vcc , q => q1, clk => clk, clrn => q0 , prn => vcc);
process (clk)
begin
if clk'event and clk='1' then
d0 <= not q1;
d1 <= d0;
end if ;
end process ;
d_out <= not (d1 and not d0);
end a;
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