run.vhd

可以实现IO口在微处理器上的扩展

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;

entity runled is
port(clk:in std_logic;
     put:out std_logic_vector(6 downto 0));
end entity runled;

architecture led of runled is
signal start:std_logic;
signal counter1:integer range 0 to 56;
signal sta_cont:std_logic;
signal counter2:integer range 0 to 2;
signal shift:std_logic_vector(6 downto 0);
begin
star:process(clk)
begin
if(clk'event and clk='1') then
  case start is
  when '0'=>if(counter1<56)then
              counter1<=counter1+1;
              shift<="1111110";
            elsif(counter1=56)then
              start<='1';
            end if;
  when '1'=>if (sta_cont='0')then
              if(counter2<2)then
                 counter2<=counter2+1;
              elsif(counter2=2)then
                 sta_cont<='1';
                 counter2<=0;
              end if;
            elsif(sta_cont='1')then
              for i in 1 to 6 loop
                shift(i)<=shift(i-1);
              end loop;
              shift(0)<=shift(6);
                sta_cont<='0';
            end if;
   end case;
end if;
end process;
put<=shift;
end architecture led;