divider.vhd

来自「VHDL实现的示波器-完整的文档和源代码」· VHDL 代码 · 共 51 行

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity last is
    Port ( sel : in std_logic_vector(3 downto 0);
           clk : in std_logic;
--           clkbar: out std_logic;
			  clok : out std_logic);
end last;

architecture Behavioral of last is
signal temp : std_logic_vector(13 downto 0) ;
signal clock : std_logic;
begin

A:process(clk) 

	begin
		if(clk'event and clk='1') then
			temp <= temp + 1;
		end if;
end process;

B: process(temp) 
	begin

	case sel is
		when "0000" => clock <= temp(2);
 	   when "0001" => clock <= temp(3);
		when "0010" => clock <= temp(4);
		when "0011" => clock <= temp(5);
		when "0100" => clock <= temp(6);
		when "0101" => clock <= temp(7);
		when "0110" => clock <= temp(8);
		when "0111" => clock <= temp(9);
		when "1000" => clock <= temp(10);
		when "1001" => clock <= temp(11);
		when "1010" => clock <= temp(12);
		when "1011" => clock <= temp(13);
		when others			  => clock <= clk;
	end case;
	clok <=clock;
--	clkbar<=not clock;
end process;

end Behavioral;