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Logic Analyzer 的代码
colour.vhd
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
entity colour is
port (
key1:in std_logic;
color:buffer integer range
colour.vhd
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
entity colour is
port (
key1:in std_logic;
color:buffer integer range
colour.vhd.bak
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
entity colour is
port (
key1:in std_logic;
color:buffer integer
a244.vhd
library ieee;
use ieee.std_logic_1164.all;
entity A244 is
port (GN1,GN2 : IN std_logic;
A1,A2 : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
Y1,Y2 : OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
END
a138.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY A138 IS
PORT (G1,G2AN,G2BN : IN STD_LOGIC;
A, B, C : IN STD_LOGIC;
YN : OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
END A138
aes encryption.txt
--头文件
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilin
serial.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
-- Uncomment the following lines to use the declarations that are
-- provided for instantia
interface.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for instantia
mux.vhd
-------------------------------------------------------------------------------
-- Title : mux
-- Project :
-------------------------------------------------------------------------------
--
conj.vhd
-------------------------------------------------------------------------------
-- Title : Conj.vhd
-- Project :
------------------------------------------------------------------------------