📄 aes encryption.txt
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--头文件
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity aes is
PORT(
plaintext : IN STD_LOGIC_VECTOR(127 DOWNTO 0);
user_key : IN STD_LOGIC_VECTOR(127 DOWNTO 0);
ciphertext : OUT STD_LOGIC_VECTOR(127 DOWNTO 0);
encrypt : IN STD_LOGIC;
clk : IN STD_LOGIC;
reset : IN STD_LOGIC
);
end aes;
architecture Behavioral of aes is
COMPONENT round
PORT(
e_in : IN STD_LOGIC_VECTOR(127 DOWNTO 0);
key : IN STD_LOGIC_VECTOR(127 DOWNTO 0);
last_mux_sel: IN STD_LOGIC;
d_out : OUT STD_LOGIC_VECTOR(127 DOWNTO 0)
);
END COMPONENT;
COMPONENT key_scheduel
PORT(
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
key_in : IN STD_LOGIC_VECTOR(127 DOWNTO 0);
key_out : OUT STD_LOGIC_VECTOR(127 DOWNTO 0);
key_reg_mux_sel : IN STD_LOGIC;
round_constant : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
load_key_reg : IN STD_LOGIC
);
END COMPONENT;
COMPONENT control
PORT(
reset : IN STD_LOGIC;
clk : IN STD_LOGIC;
encrypt : IN STD_LOGIC;
data_reg_mux_sel: OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
load_data_reg : OUT STD_LOGIC;
key_reg_mux_sel : OUT STD_LOGIC;
round_const : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
last_mux_sel : OUT STD_LOGIC;
load_key_reg : OUT STD_LOGIC
);
END COMPONENT;
--signals declaration
SIGNAL data_reg_in, data_reg_out, round0_out, round1_10_out,
key: STD_LOGIC_VECTOR(127 DOWNTO 0);
SIGNAL key_reg_mux_sel : std_logic;
SIGNAL round_constant : std_logic_vector(7 downto 0);
SIGNAL data_reg_mux_sel : std_logic_vector(1 downto 0);
SIGNAL load_data_reg, load_key_reg, last_mux_sel : std_logic;
BEGIN
WITH data_reg_mux_sel SELECT
data_reg_in <= round0_out WHEN "00",
round1_10_out WHEN "01",
plaintext WHEN OTHERS;
round0_out <= data_reg_out XOR key;
layers: round
PORT MAP(
e_in => data_reg_out,
key => key,
last_mux_sel=> last_mux_sel,
d_out => round1_10_out
);
data_register:
PROCESS(clk, reset, load_data_reg, data_reg_in)
BEGIN
IF(reset='1') THEN
data_reg_out <= "0000000000000000000000000000000000000000000"&
"0000000000000000000000000000000000000000000"&
"000000000000000000000000000000000000000000";
ELSIF(clk'event AND clk='1') THEN
IF(load_data_reg='1') THEN
data_reg_out <= data_reg_in;
END IF;
END IF;
END PROCESS data_register;
key_generator: key_scheduel
PORT MAP(
clk => clk,
reset => reset,
key_in => user_key,
key_out => key,
key_reg_mux_sel => key_reg_mux_sel,
round_constant => round_constant,
load_key_reg => load_key_reg
);
contrl: control
PORT MAP(
reset => reset,
clk => clk,
encrypt => encrypt,
data_reg_mux_sel=> data_reg_mux_sel,
load_data_reg => load_data_reg,
key_reg_mux_sel => key_reg_mux_sel,
round_const => round_constant,
last_mux_sel => last_mux_sel,
load_key_reg => load_key_reg
);
ciphertext <= data_reg_out;
end Behavioral;
--密钥扩展
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity key_scheduel is
PORT(
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
key_in : IN STD_LOGIC_VECTOR(127 DOWNTO 0);
key_out : OUT STD_LOGIC_VECTOR(127 DOWNTO 0);
key_reg_mux_sel : IN STD_LOGIC;
round_constant : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
load_key_reg : IN STD_LOGIC
);
end key_scheduel;
architecture Behavioral of key_scheduel is
COMPONENT s_box_4
PORT(
s_word_in : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_word_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT;
--signal declaration
TYPE word_array is array (3 downto 0) of std_logic_vector(31 downto 0);
SIGNAL key_word, next_key_word : word_array;
SIGNAL T , temp_shift, temp_sbox: std_logic_vector(31 downto 0);
SIGNAL key_reg_in, next_key, key_reg_out : std_logic_vector(127 downto 0);
SIGNAL upperbyte_trans : std_logic_vector(7 downto 0);
BEGIN
--key register, which stores a round key:
key0:
PROCESS(reset, clk, key_reg_in, load_key_reg)
BEGIN
IF(reset='1') THEN
key_reg_out <= "00000000000000000000000000000000000000000000"&
"00000000000000000000000000000000000000000000"&
"0000000000000000000000000000000000000000";
ELSIF(clk'event AND clk='1') THEN
IF(load_key_reg='1') THEN
key_reg_out <= key_reg_in;
END IF;
END IF;
END PROCESS key0;
--mux at the input of key register
key_reg_in <= key_in WHEN key_reg_mux_sel='0' ELSE --original key, 1st round
next_key; --for following rounds
--mapping a vector into array of words
key_word(0) <= key_reg_out(127 downto 96);
key_word(1) <= key_reg_out(95 downto 64);
key_word(2) <= key_reg_out(63 downto 32);
key_word(3) <= key_reg_out(31 downto 0);
--calculating next key words or next key column
next_key_word(0) <= key_word(0) XOR T;
next_key_word(1) <= key_word(1) XOR key_word(0) XOR T;
next_key_word(2) <= key_word(2) XOR key_word(1) XOR key_word(0) XOR T;
next_key_word(3) <= key_word(3) XOR key_word(2) XOR key_word(1) XOR key_word(0) XOR T;
--converting word array back to a vector
next_key <= next_key_word(0) & next_key_word(1) & next_key_word(2) & next_key_word(3);
--below describes the calculation of T:
--left shift
temp_shift <= key_word(3)(23 downto 16) &
key_word(3)(15 downto 8) &
key_word(3)(7 downto 0) &
key_word(3)(31 downto 24);
--key subbyte transformation
sbox_lookup: s_box_4
PORT MAP(
s_word_in => temp_shift,
s_word_out => temp_sbox
);
--XOR the upperbyte and round constant
upperbyte_trans <= temp_sbox(31 downto 24) XOR round_constant;
--finally vector T calculated
T <= upperbyte_trans & temp_sbox(23 downto 0);
--connecting signal to a entity port
key_out <= key_reg_out;
end Behavioral;
--round模块
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity round is
PORT(
e_in : IN STD_LOGIC_VECTOR(127 DOWNTO 0);
key : IN STD_LOGIC_VECTOR(127 DOWNTO 0);
last_mux_sel: IN STD_LOGIC;
d_out : OUT STD_LOGIC_VECTOR(127 DOWNTO 0)
);
end round;
architecture Behavioral of round is
COMPONENT s_box
--s_box in relation to operation subyte
PORT(
s_box_in : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_box_out : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
COMPONENT shift_row
--in relation to operation shift_row
PORT(
shiftrow_in : IN STD_LOGIC_VECTOR(127 DOWNTO 0);
shiftrow_out : OUT STD_LOGIC_VECTOR(127 DOWNTO 0)
);
END COMPONENT;
COMPONENT mix_column
--in relation to operation mix_column
PORT(
mixcolumn_in : IN STD_LOGIC_VECTOR(127 DOWNTO 0);
mixcolumn_out : OUT STD_LOGIC_VECTOR(127 DOWNTO 0)
);
END COMPONENT;
SIGNAL bytesub_out, shiftrow_out, mixcolumn_out, mux_out : STD_LOGIC_VECTOR(127 DOWNTO 0);
--signal declaration
BEGIN
--16 replica of 8-bit S-box is generated
sboxes:
FOR i IN 15 DOWNTO 0 GENERATE
sbox_map: s_box
port map(
s_box_in => e_in(8*i+7 downto 8*i),
s_box_out => bytesub_out(8*i+7 downto 8*i)
);
END GENERATE sboxes;
ShiftRow: shift_row
PORT MAP(
shiftrow_in => bytesub_out,
shiftrow_out => shiftrow_out
);
MixColumn: mix_column
PORT MAP(
mixcolumn_in => shiftrow_out,
mixcolumn_out => mixcolumn_out
);
--mux to skip mix column operation
WITH last_mux_sel SELECT
mux_out <= mixcolumn_out WHEN '0',
shiftrow_out WHEN OTHERS;
--round key addition
d_out <= mux_out XOR key;
end Behavioral;
--控制模块
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity control is
PORT(
reset : IN STD_LOGIC;
clk : IN STD_LOGIC;
encrypt : IN STD_LOGIC;
data_reg_mux_sel: OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
load_data_reg : OUT STD_LOGIC;
key_reg_mux_sel : OUT STD_LOGIC;
round_const : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
last_mux_sel : OUT STD_LOGIC;
load_key_reg : OUT STD_LOGIC
);
end control;
architecture Behavioral of control is
TYPE control_type IS (init, load_inputs, round1, round2, round3, round4, round5,
round6, round7, round8, round9, round10, round0);
SIGNAL control_ps, control_ns : control_type;
BEGIN
--finite state machine for control
control_FSM:
PROCESS (clk, encrypt, reset, control_ns, control_ps)
BEGIN
IF(reset='1') THEN
control_ps <= init;
ELSIF (clk'event AND clk='1') THEN
control_ps <= control_ns;
END IF;
key_reg_mux_sel <= '1';
data_reg_mux_sel <= "01";
round_const <= "00000000";
load_key_reg <= '1';
load_data_reg <= '1';
last_mux_sel <= '0';
--combinatorial part
CASE control_ps IS
WHEN init =>
key_reg_mux_sel <= '0';
load_key_reg <= '0';
load_data_reg <= '0';
IF (encrypt='1') THEN
control_ns <= load_inputs;
ELSE
control_ns <= init;
END IF;
WHEN load_inputs =>
data_reg_mux_sel <= "11";
key_reg_mux_sel <= '0';
control_ns <= round0;
--key0 loaded, XOR key0 and plaintext
WHEN round0 =>
round_const <= "00000001";
data_reg_mux_sel <= "00";
control_ns <= round1;
--key
WHEN round1 =>
round_const <= "00000010";
control_ns <= round2;
--key2
WHEN round2 =>
round_const <= "00000100";
control_ns <= round3;
--key3
WHEN round3 =>
round_const <= "00001000";
control_ns <= round4;
--key4
WHEN round4 =>
round_const <= "00010000";
control_ns <= round5;
--key5
WHEN round5 =>
round_const <= "00100000";
control_ns <= round6;
--key6
WHEN round6 =>
round_const <= "01000000";
control_ns <= round7;
--key7
WHEN round7 =>
round_const <= "10000000";
control_ns <= round8;
--key8
WHEN round8 =>
round_const <= "00011011";
control_ns <= round9;
--key9
WHEN round9 =>
round_const <= "00110110";
control_ns <= round10;
--key10, last round excludes the mix column step
WHEN round10 =>
last_mux_sel <= '1';
load_key_reg <= '0';
control_ns <= init;
END CASE;
END PROCESS control_FSM;
end Behavioral;
--S盒
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity s_box is
PORT(
s_box_in : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_box_out : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
end s_box;
architecture Behavioral of s_box is
begin
WITH s_box_in(7 DOWNTO 0) SELECT
--including 16 groups
s_box_out(7 DOWNTO 0) <=
--the 1st group
"01100011" WHEN "00000000", --(X"63")
"01111100" WHEN "00000001", --(X"7C")
"01011110" WHEN "00000010", --(X"5D")
"01000010" WHEN "00000011", --(X"42")
"00011111" WHEN "00000100", --(X"1F")
"00000000" WHEN "00000101", --(X"00")
"00100001" WHEN "00000110", --(X"21")
"00111110" WHEN "00000111", --(X"3E")
"10011011" WHEN "00001000", --(X"9B")
"10000100" WHEN "00001001", --(X"84")
"10100101" WHEN "00001010", --(X"A5")
"10111010" WHEN "00001011", --(X"BA")
"11100111" WHEN "00001100", --(X"E7")
"11111000" WHEN "00001101", --(X"F8")
"11011001" WHEN "00001110", --(X"D9")
"11000110" WHEN "00001111", --(X"C6")
--the 2st group
"10010010" WHEN "00010000", --(X"92")
"10001101" WHEN "00010001", --(X"8D")
"10101100" WHEN "00010010", --(X"AC")
"10110011" WHEN "00010011", --(X"B3")
"11101110" WHEN "00010100", --(X"EE")
"11110001" WHEN "00010101", --(X"F1")
"11100000" WHEN "00010110", --(X"D0")
"11001111" WHEN "00010111", --(X"CF")
"01101010" WHEN "00011000", --(X"6A")
"01110101" WHEN "00011001", --(X"75")
"01010100" WHEN "00011010", --(X"54")
"01001011" WHEN "00011011", --(X"4B")
"00010110" WHEN "00011100", --(X"16")
"00001001" WHEN "00011101", --(X"09")
"00101000" WHEN "00011110", --(X"28")
"00110111" WHEN "00011111", --(X"37")
--the 3st group
"10000000" WHEN "00100000", --(X"80")
"10011111" WHEN "00100001", --(X"9F")
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