a244.vhd

vhdl语言程序的a244器件的程序 希望对大家的学习有所帮助

library ieee;
use ieee.std_logic_1164.all;

entity A244 is
port (GN1,GN2 : IN std_logic;
      A1,A2   : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
      Y1,Y2   : OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
END A244;

ARCHITECTURE RTL OF A244 IS
BEGIN
PROCESS ( GN1, GN2)
  BEGIN
  IF (GN1='0' AND GN2='0') THEN
    Y1<=A1;
    Y2<=A2;
  ELSIF (GN1='1' AND GN2='1') THEN
    Y1<="ZZZZ";
    Y2<="ZZZZ";
  END IF;
END PROCESS;
END RTL;