a374.vhd

来自「vhdl语言程序的a244器件的程序 希望对大家的学习有所帮助」· VHDL 代码 · 共 22 行

library ieee;
use ieee.std_logic_1164.all;

entity a374 is
port (clk : in std_logic;
      oen : in std_logic;
        d : in std_logic_vector(7 downto 0);
        q : out std_logic_vector(7 downto 0));
end a374;

architecture rtl of a374 is
begin
process (clk,oen)
  begin
    if (oen='1') then
         q<="ZZZZZZZZ";
    elsif (clk'event and clk='1') then
         q<=d;
    end if;
    
end process;
end rtl;