a138.vhd

来自「vhdl语言程序的a244器件的程序 希望对大家的学习有所帮助」· VHDL 代码 · 共 37 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

ENTITY A138 IS
PORT (G1,G2AN,G2BN : IN STD_LOGIC;
       A,   B,   C : IN STD_LOGIC;
       YN          : OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
END A138;

ARCHITECTURE  RTL OF A138 IS
  SIGNAL G2N: STD_LOGIC;
  SIGNAL INDATA:STD_LOGIC_VECTOR(2 DOWNTO 0);
BEGIN
  INDATA<=C & B & A;
 -- G1<='1';
  G2N<= G2AN OR G2BN;
PROCESS (INDATA, G1,G2N)
  BEGIN
    IF (G1='1' AND G2N='0') THEN
       CASE INDATA IS
            WHEN "000" =>YN<="11111110";
            WHEN "001" =>YN<="11111101";
            WHEN "010" =>YN<="11111011";
            WHEN "011" =>YN<="11110111";
            WHEN "100" =>YN<="11101111";
            WHEN "101" =>YN<="11011111";
            WHEN "110" =>YN<="10111111";
            WHEN "111" =>YN<="01111111";
            WHEN OTHERS=>YN<="XXXXXXXX";
       END CASE;
    ELSE
      YN<="11111111";
    END IF;
END PROCESS;
END RTL;