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Logic Analyzer 的代码
updown2.vhd
-- updown2 模块(of testup_f_k)
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity updown2 is
port(
r_in:in std_logic;
gh_tvfd_filter.vhd
---------------------------------------------------------------------
-- Filename: gh_TVFD_filter.vhd
--
-- Description:
-- Time Varying Fractional Delay Filter
--
-- Copyright (c) 2005, 20
compressor_tb.vhd
---------------------------------------------------------------------------------------------------
--
-- Title : JPEG Hardware Compressor Testbench
-- Design : jpeg
-- Author : Vi
mux8.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity mux8 is
port(
a,b,c,d,e,f:in std_logic_vector(3 downto 0);
clk:in std_logi
seven.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
ENTITY seven IS
PORT
( men: IN std_logic_vector(6 downto 0);
pass: buffer std_logic
);
END seven;
ARCHITECTURE beha
temp.vhd.bak
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity temp is
port(
p : out std_logic;
reset: in std_logic;
temp.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity temp is
port(
p : out std_logic;
reset: in std_logic;
saomiao.txt
library ieee;
use ieee.std_logic_1164.all;
entity saomiao is
port(clk:in std_logic;
d3,d2,d1,d0:in std_logic_vector(3 downto 0);
q:out std_logic_vector(3 downto 0);
stime.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for ins
leijiaqi.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_signed.all;
entity leijiaqi is
port(clk:in std_logic;
y:out std_logic);
end;
architecture main of leijiaqi is
signal